Program Counter–ROM–Instruction Register Fetch Simulator

Fig. 1 — Program Counter–ROM–Instruction Register Fetch PathInteractive simulation

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What You'll Learn

Trace the implemented PC → ROM → instruction-register fetch path.
Apply the PC's fixed increment, load, reset, and output-enable controls.
Explain the registered one-edge relationship between the addressed ROM byte and IR.
Interpret the low-nibble displays and IR-bit-0 light correctly.
Identify the decode and execute subsystems absent from this topology.

How It Works

The production circuit is a clocked instruction-fetch path, not a complete instruction executor. An 8-bit program counter drives the eight ROM address inputs. PC increment and output enable are tied to 1; PC load and reset are tied to 0. Every rising edge therefore increments the PC modulo 256.

ROM chip select and output enable are active low and tied to 0, so the selected byte continuously drives the eight instruction-register data inputs. The instruction register's load input is tied high and it shares CLK with the PC. It captures the pre-edge addressed ROM byte while the PC advances; subsequent combinational propagation changes the ROM output for the next edge.

The saved PC state is 0xB9 and the saved IR is 0x00. ROM addresses 0, 1, 2, and 3 contain 0x01, 0x02, 0x03, and 0x00; all remaining addresses contain 0x00. One display shows PC[3:0], another shows IR[3:0], and one light shows IR bit 0. There is no decode, control, ALU, branch, or execution path.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
Clock=inspect saved state before next rising edge
Expected:Saved PC = 0xB9, PC display = 9, IR = 0x00, instruction display = 0, light off
What you'll see:Before advancing the saved circuit, inspect the state fields and visible indicators. Only each low nibble is displayed, so PC 0xB9 appears as 9.
2
Clock=1 rising edge
Expected:PC = 0xBA while IR remains 0x00
What you'll see:Apply one rising edge. PC increments to 0xBA; ROM at the previous and new high addresses contains 0, so IR remains 0x00.
3
Clock=70 additional rising edges
Expected:PC wraps to 0x00 while IR remains 0x00
What you'll see:Apply 70 more rising edges. This makes 71 edges from the saved 0xB9 state, wrapping PC to 0x00; IR still contains the byte from address FF, which is 0.
4
Clock=1 additional rising edge
Expected:PC = 0x01 and IR captures ROM[0] = 0x01; the instruction light turns on
What you'll see:Apply one further rising edge. IR captures ROM[0] = 0x01 while PC advances to 0x01, so the instruction display reads 1 and the IR-bit-0 light turns on.

Components Used

Clock

×1

Role: Clocks both the program counter and instruction register.

Program Counter (8-bit)

×1

Role: Generates the sequential eight-bit ROM address and wraps modulo 256.

ROM

×1

Role: Continuously reads the byte selected by the program-counter address.

Instruction Register

×1

Role: Captures the ROM byte on each rising edge; only its low-nibble outputs are used.

Output Light

×1

Role: Displays instruction-register bit 0.

Digit Display

×2

Role: Displays the low nibble of the PC and the low nibble of the instruction register.

Logic-1 Constant

×1

Role: Holds PC increment, PC output enable, and instruction-register load high.

Logic-0 Constant

×3

Role: Holds PC load and reset low and enables the ROM's active-low CS and OE inputs.

Applications and Design Context

Instruction fetch front ends. Program counters and instruction memories form the address-and-read portion of a processor front end.

ROM sequencers. A counter can step through fixed control or lookup bytes without decoding them in this circuit.

Registered memory outputs. Capturing a combinational ROM output creates a stable byte for a later, separately implemented stage.

Architecture instruction. The topology cleanly separates fetch from the decode and execute blocks that a complete CPU would require.

Frequently Asked Questions

Does this circuit decode or execute instructions?

No. The production topology contains a program counter, ROM, and instruction register, but no control unit, opcode decoder, ALU, general-purpose register file, data bus, or write-back path.

How is the program counter controlled?

The 8-bit program counter drives ROM address A0..A7. INC and output enable are tied high; load and reset are tied low. It increments on every rising clock edge and wraps from FF to 00.

What is stored in ROM?

ROM CS and OE are active low and both tied to 0, so ROM continuously drives the byte at the current PC address. The saved memory begins 01, 02, 03, 00 at addresses 0–3; later locations are 00.

When does the instruction register load?

IR load is tied high and it shares the clock with the PC. On each rising edge it captures the ROM byte present before the PC output propagates to the next address. This gives a one-edge registered fetch relationship.

What do the displays and light show?

The PC display receives only PC bits 0–3, and the instruction display receives only IR bits 0–3. The output light receives IR bit 0. High nibbles are not numerically displayed.