XOR and XNOR Gate-Level Comparison
Gate-level networks are compared with packaged XOR and XNOR components across two independent input pairs. The visible outputs distinguish equality from difference without implying identical physical implementations.
What You'll Learn
- Derive XOR from the two unequal-input minterms.
- Derive XNOR from the two equal-input minterms.
- Compare gate-level networks with packaged XOR and XNOR components.
- Recognize that the left and right demonstrations use independent switch pairs.
- Relate XOR to parity and XNOR to equality detection.
How It Works
This production circuit presents two parallel demonstrations. The left side constructs XOR and XNOR from NOT, AND, and OR gates driven by one switch pair. The right side drives packaged XOR and XNOR components from a second, independent switch pair. Four output lights make the results visible.
For the gate-level pair, XOR ORs the unequal-input minterms A_gate·¬B_gate and ¬A_gate·B_gate. XNOR ORs the equal-input minterms A_gate·B_gate and ¬A_gate·¬B_gate. Two NOT gates are shared by those left-side constructions, but the XOR and XNOR outputs each have their own two AND gates and OR gate.
The built-in gates implement the same two Boolean functions for A_builtin and B_builtin. Because the right switches are not wired to the left networks, a side-by-side equality check requires assigning both pairs the same vector. Deliberately assigning different vectors demonstrates that the four lights are not four views of one shared input.
Truth Table
The four physical switches form two independent pairs. The first four rows apply matching vectors to both pairs; the final rows deliberately separate them to expose the independent wiring.
| Inputs | Output | |||||||
|---|---|---|---|---|---|---|---|---|
| A_gate | B_gate | A_builtin | B_builtin | XOR_gate | XNOR_gate | XOR_builtin | XNOR_builtin | |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | Both pairs are equal at 00, so both XNOR outputs are high |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | Both pairs differ at 01, so both XOR outputs are high |
| 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | Both pairs differ at 10, giving the same complementary result |
| 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | Both pairs are equal at 11, so both XNOR outputs are high |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | The gate-level pair is equal while the built-in pair differs |
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | The gate-level pair differs while the built-in pair is equal |
Boolean Expression
The left XOR network ORs the two minterms for unequal gate-level inputs.
The left XNOR network ORs the two minterms for equal gate-level inputs.
The built-in XOR applies the same difference function to a separate input pair.
The built-in XNOR applies the complementary equality function to that separate pair.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A_builtin=0A_gate=0B_builtin=0B_gate=0Expected:
XOR_gate = 0, XNOR_gate = 1; XOR_builtin = 0, XNOR_builtin = 1What you'll see:With 00 on both pairs, the two equality outputs are high and the two difference outputs are low. - 2A_builtin=0A_gate=0B_builtin=1B_gate=1Expected:
XOR_gate = 1, XNOR_gate = 0; XOR_builtin = 1, XNOR_builtin = 0What you'll see:With 01 on both pairs, the gate-level and built-in implementations show the same XOR-high result. - 3A_builtin=1A_gate=1B_builtin=1B_gate=0Expected:
XOR_gate = 1, XNOR_gate = 0; XOR_builtin = 0, XNOR_builtin = 1What you'll see:The left pair 10 differs, but the right pair 11 is equal; the two sections intentionally report different results. - 4A_builtin=0A_gate=1B_builtin=1B_gate=1Expected:
XOR_gate = 0, XNOR_gate = 1; XOR_builtin = 1, XNOR_builtin = 0What you'll see:The left pair 11 is equal, while the right pair 01 differs, confirming that their switches are independent.
Components Used
Applications and Design Context
Adder sum logic. A half adder uses A ⊕ B for Sum, and a full adder extends the parity calculation to include Cin.
Equality comparison. XNOR produces a per-bit match signal; combining those signals determines whether two words are equal.
Parity generation and checking. XOR reduction computes odd parity and supports simple transmission-error checks.
Controlled inversion. XOR with a control bit passes a signal when the control is 0 and inverts it when the control is 1, a pattern used in add/subtract datapaths.
Logic synthesis education. Comparing an explicit sum-of-products network with a packaged primitive separates Boolean equivalence from physical cell implementation.
Frequently Asked Questions
How is the left XOR output constructed?
The gate-level XOR forms A_gate·¬B_gate and ¬A_gate·B_gate with two NOT gates, two AND gates, and one OR gate. Those are exactly the two input assignments in which the operands differ.
Do all four outputs share the same input pair?
No. The gate-level network uses A_gate and B_gate, while the packaged components use A_builtin and B_builtin. The outputs agree only when the two input pairs are assigned the same values.
Is XNOR always the inverse of XOR?
For any one input pair, XNOR is the logical complement of XOR: unequal inputs make XOR high, whereas equal inputs make XNOR high. On this canvas the two functions are implemented as separate networks rather than by wiring a NOT gate after the XOR output.
Where are XOR and XNOR used?
XOR is the sum bit of one-bit addition without carry and generalizes to odd parity across multiple inputs. XNOR is a one-bit equality test; a wider equality comparator AND-reduces one XNOR result per bit position.
Are the packaged gates physically identical to the left networks?
The packaged gates state only the Boolean interface. A library may implement them with static CMOS, transmission gates, pass-transistor logic, or a technology-specific cell. The left networks show a canonical sum-of-products construction, not a transistor-level implementation.