Level-Sensitive D Latch
A packaged D latch follows D while Enable is HIGH and retains the previously accepted bit while Enable is LOW. Two lights expose Q and its complement.
What You'll Learn
- Recognize the D latch as a single-data-input memory element.
- Understand how the D latch eliminates the SR latch's forbidden state.
- Distinguish transparent mode (enable = 1, Q follows D) from hold mode (enable = 0, Q frozen).
- Connect the D latch's structure to its underlying SR latch.
- Identify D latches as basic building blocks for registers.
How It Works
This circuit contains two input switches, one packaged D latch, and two output lamps. The Data switch drives D; the Enable switch drives the latch's level-sensitive enable input. The lamps display Q and ¬Q.
When Enable = 1, the latch is transparent: Q follows D after propagation delay. When Enable = 0, the latch is in hold mode: changes at D do not change Q, and the previously captured bit remains stored. Its characteristic equation is Qnext = Enable·D + ¬Enable·Q.
A conventional gated D latch derives mutually exclusive set and reset controls from D and ¬D while Enable is active. This avoids the simultaneously asserted set/reset condition of a basic active-high SR latch. The packaged component exposes the resulting behavior rather than the internal gates.
Because it is level-sensitive, the latch may respond to every D transition during the entire enabled interval. Edge-triggered D flip-flops add timing structure so that sampling occurs only at a clock edge. Arrays of latches or flip-flops form multi-bit registers.
Truth Table
Qprev is the stored state before evaluation. Enable=0 preserves Qprev regardless of D; Enable=1 makes Qnext equal D.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| E | D | Qprev | Q | ¬Q | |
| 0 | 0 | 0 | 0 | 1 | Hold 0; D is LOW but ignored while Enable is LOW. |
| 0 | 0 | 1 | 1 | 0 | Hold 1; D is LOW but ignored while Enable is LOW. |
| 0 | 1 | 0 | 0 | 1 | Hold 0; D is HIGH but ignored while Enable is LOW. |
| 0 | 1 | 1 | 1 | 0 | Hold 1; D is HIGH but ignored while Enable is LOW. |
| 1 | 0 | 0 | 0 | 1 | Transparent mode captures D=0, clearing Q. |
| 1 | 0 | 1 | 0 | 1 | Transparent mode keeps Q LOW because D=0. |
| 1 | 1 | 0 | 1 | 0 | Transparent mode captures D=1, setting Q. |
| 1 | 1 | 1 | 1 | 0 | Transparent mode keeps Q HIGH because D=1. |
Boolean Expression
When Enable is HIGH, the D term determines the next state. When Enable is LOW, the feedback term preserves the current Q value.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1D=0Enable=1Expected:
Q = 0, ¬Q = 1What you'll see:With Enable HIGH and D LOW, the transparent latch clears Q and asserts ¬Q. - 2D=1Enable=1Expected:
Q = 1, ¬Q = 0What you'll see:Keep Enable HIGH and set D HIGH. Q follows D and becomes HIGH. - 3D=0Enable=0Expected:
Q remains 1, ¬Q remains 0What you'll see:Set Enable LOW, then return D to LOW. Q remains HIGH, demonstrating stored state rather than buffer behavior. - 4D=0Enable=1Expected:
Q = 0, ¬Q = 1What you'll see:Reassert Enable while D is LOW. The latch becomes transparent again and Q clears.
Components Used
Applications and Design Context
Captured decoder outputs. Decoder outputs can be captured by latches after the address has settled so that transition glitches are not propagated as multiple chip-select pulses. The capture control must remain inactive while the address is changing.
Processor pipeline storage. Latch-based and edge-triggered register structures are both used in processor pipelines; the choice depends on the clocking methodology, timing-closure strategy, and implementation technology. Either can hold values between pipeline stages.
Configuration register storage. Configuration bits set during initialization can use D latches with a one-time enable pulse to freeze the value.
Holding peripheral data. A peripheral whose output bus is read once per cycle can use D latches with the bus-strobe as enable.
Educational stepping stone. D latches are introduced before D flip-flops because they're simpler internally — once you understand transparency vs. holding, edge triggering follows naturally.
Frequently Asked Questions
Is Enable the same as a clock edge?
Enable is a level-sensitive gate, not an edge-triggered clock. While Enable is HIGH, Q can follow changes at D throughout the enabled interval. When Enable goes LOW, the last captured value is held. An edge-triggered D flip-flop instead samples only at a clock transition.
How does this eliminate SR's forbidden state?
In a conventional gated D latch built around an active-high SR stage, S = Enable·D and R = Enable·¬D. When Enable=1, S and R are complementary; when Enable=0, both are LOW and the SR stage holds its state. They are therefore never both HIGH, so S=R=1 is structurally unreachable.
What's the practical difference between this and a buffer?
With Enable HIGH, both pass D after propagation delay. With Enable LOW, this latch retains its previous Q value while a buffer would continue to follow its input. The hold state is the essential difference.
Why include both Q and ¬Q outputs?
Symmetry from the underlying SR latch. Many circuits want both polarities — saves an external inverter. ¬Q is also called Q-bar or Q-prime in textbooks.
How does this scale to multi-bit storage?
An N-bit register can use N D latches in parallel with a shared enable. Each latch stores one bit independently. Such arrays are building blocks for many registers and register files, although implementations may instead use flip-flops or dedicated memory-cell structures.