4-Bit Ring Counter Circuit Simulator

Fig. 1 — 4-Bit Ring CounterInteractive simulation

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A ring counter is a circular shift register. This 4-bit version circulates one asserted bit through four D flip-flops to produce a one-hot four-state sequence.

What You'll Learn

Connect D flip-flops as a circular synchronous shift path.
Initialize a one-hot state with asynchronous preset and clear inputs.
Trace the four-state 1000 → 0100 → 0010 → 0001 sequence.
Explain the direct-decode advantage and state-capacity cost of one-hot counting.
Predict the behavior of all-zero and multiple-one initial states.

How It Works

The Q output of each D flip-flop feeds the D input of the next stage, and Q3 feeds D0 to close the loop. All four stages share one clock, so every state transition occurs synchronously on the same rising edge. With signals written in the displayed order Q0 Q1 Q2 Q3, the intended cycle is 1000 → 0100 → 0010 → 0001 → 1000.

A ring counter must be initialized to a useful state. In this circuit, asserting Preset asynchronously sets Q0 and clears Q1, Q2, and Q3, loading 1000. Release Preset before clocking; if it remains asserted, the asynchronous controls continue to force the initial state.

The one-hot sequence uses four flip-flops for four states, which is less state-dense than an ordinary binary counter but makes individual phases directly available. No binary decoder is needed to select one of the four phase outputs. The counter is not self-correcting: starting at 0000 would keep it at 0000, while a state with multiple 1s would circulate multiple asserted bits.

Truth Table

This is a state-transition table, not a combinational truth table. Current and next-state vectors use the circuit's displayed order Q0 Q1 Q2 Q3 and assume Preset is released before the rising edge.

Inputs				Output
Current Q0	Current Q1	Current Q2	Current Q3	Next Q0	Next Q1	Next Q2	Next Q3
1	0	0	0	0	1	0	0	The preset state advances from Q0 to Q1.
0	1	0	0	0	0	1	0	The asserted bit advances from Q1 to Q2.
0	0	1	0	0	0	0	1	The asserted bit advances from Q2 to Q3.
0	0	0	1	1	0	0	0	Feedback from Q3 returns the asserted bit to Q0.

Boolean Expression

Q_0^{+} = Q_3

The last stage feeds the first stage on the next active edge.

Q_1^{+} = Q_0

Q0 advances into Q1.

Q_2^{+} = Q_1

Q1 advances into Q2.

Q_3^{+} = Q_2

Q2 advances into Q3.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
Clock=0Preset=1
Expected:Q0 Q1 Q2 Q3 = 1000
What you'll see:Preset forces the intended one-hot seed: Q0 is HIGH and the remaining outputs are LOW.
2
Clock=first rising edgePreset=0
Expected:Q0 Q1 Q2 Q3 = 0100
What you'll see:After Preset is released, one rising edge transfers the asserted bit from Q0 to Q1.
3
Clock=second rising edgePreset=0
Expected:Q0 Q1 Q2 Q3 = 0010
What you'll see:The next edge transfers the bit from Q1 to Q2; all flip-flops update from the previous state simultaneously.
4
Clock=third and fourth rising edgesPreset=0
Expected:The sequence passes through 0001 and returns to 1000
What you'll see:Two more edges move the bit through Q3 and back to Q0, completing a four-clock period.

Components Used

Input Switch

×2

Role: One switch supplies the clock; a second drives the shared initialization network labeled Preset.

D Flip-Flop

×4

Role: Four stages retain and synchronously advance the circulating one-hot state.

Output Light

×4

Role: Four indicators expose Q0 through Q3 as directly decoded phase outputs.

Applications and Design Context

One-hot control sequencing. Each Q output can enable one stage of a repeating four-phase process.

Stepper-motor and display scanning control. A circulating bit can select coils, rows, columns, or channels in a fixed order when the required drive pattern matches the one-hot sequence.

Round-robin scheduling. A token can circulate among requesters or time slots, with additional control logic for practical arbitration.

Timing-phase generation. Nonoverlapping conceptual phase enables are easy to identify from one-hot registered outputs.

Built-in self-test structures. Ring-like shift paths are useful for controlled scan patterns and state-observation exercises.

Frequently Asked Questions

Why is a preset operation required?

The feedback network preserves the number of asserted bits. An all-zero state remains all zero, so the intended one-hot sequence needs an initial 1000 seed.

Why must Preset be released before clocking?

Preset and clear act asynchronously on the flip-flops. While asserted, they override ordinary D-and-clock behavior and continue forcing 1000.

How many states does this ring counter provide?

The intended one-hot cycle has four states for four flip-flops. In general, an N-stage one-hot ring counter provides N directly decoded phase states.

What happens if two bits are HIGH?

Both asserted bits circulate because the circuit has no correction logic. The outputs no longer form the intended one-hot sequence until the preset operation restores 1000.

How does a ring counter differ from a Johnson counter?

A ring counter feeds the last Q output directly back to the first D input and normally circulates a seeded bit. A Johnson counter feeds back the inverted last output and produces 2N intended states from N flip-flops.