8-Bit Serial Transmitter/Receiver Circuit Simulator

Fig. 1 — 8-Bit Serial Shift PathInteractive simulation

Interactive simulator requires JavaScript

Enable JavaScript to load the circuit embed. Any available educational content remains accessible below.

Open in Full Simulator Browse All Templates

What You'll Learn

Use a PISO shift register to transmit a byte serially.
Use a SIPO shift register to receive a byte from a serial line.
Derive the LSB-first serial sequence for the fixed 0xAA word.
Verify the receiver word after exactly eight shift edges.
Identify the framing and protocol functions that this circuit does not implement.

How It Works

Fixed constants drive D7..D0 of an 8-bit transmit register to 10101010 (0xAA). Its output enable is tied high and clear is tied low. The LOAD/SHIFT switch drives both this register's load input and the transmitter SHIFT_REGISTER_8BIT's S/L input.

With LOAD/SHIFT = 1 at a rising edge, the register captures the fixed byte and the PISO stage parallel-loads its Q outputs. With LOAD/SHIFT = 0, the PISO stage right-shifts. Its SI and DIR inputs are tied to 0, so SO exposes Q0 and zeros enter Q7. The receiver's DIR and S/L inputs are permanently 0, so it right-shifts the serial line into Q7 on every rising edge.

The transmitted bit order is Q0 first: 0,1,0,1,0,1,0,1. After eight shift edges, receiver Q7..Q0 equals 10101010. Eight lights expose that receiver word. The oscilloscope shows CLK, serial data, LOAD/SHIFT, TX-register Q0, and RX Q0. No framing or error detection is implemented.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
Clock=2 rising edgesLOAD/SHIFT=1
Expected:The transmit register and PISO stage hold 0xAA
What you'll see:Set LOAD/SHIFT = 1 and apply two rising edges. The second edge guarantees that both the source register and PISO stage contain the fixed 0xAA word.
2
Clock=first shift rising edgeLOAD/SHIFT=0
Expected:The first serial bit is 0 and enters receiver Q7
What you'll see:Set LOAD/SHIFT = 0 and apply the first shift edge. The current PISO Q0 value, 0, enters receiver Q7.
3
Clock=7 additional rising edgesLOAD/SHIFT=0
Expected:Receiver Q7..Q0 = 10101010 (0xAA)
What you'll see:Apply seven additional rising edges without reasserting LOAD/SHIFT. After eight total shift edges, the receiver lights represent 0xAA.
4
Clock=1 additional rising edgeLOAD/SHIFT=0
Expected:Receiver Q7..Q0 = 01010101 (0x55)
What you'll see:Apply one more shift edge. The PISO stage has been filled with zeros, so the receiver shifts from 10101010 to 01010101.

Components Used

Load / Shift Switch

×1

Role: Drives transmit-register LOAD and PISO S/L together and feeds oscilloscope channel 3.

Clock

×1

Role: Clocks the transmit register, PISO stage, SIPO stage, and oscilloscope channel 1.

Logic-1 Constant

×3

Role: Provides the fixed 1 bits of 0xAA and holds the transmit register's output enable high.

Logic-0 Constant

×5

Role: Provides the fixed 0 bits, inactive clear, right-shift direction, serial-fill 0, and receiver shift mode.

×1

Role: Stores the fixed 0xAA source byte with output enable permanently active.

Shift Register (8-bit)

×2

Role: One instance parallel-loads and serializes 0xAA; the other shifts the serial stream into eight parallel outputs.

8-Channel Oscilloscope

×1

Role: Displays CLK, serial line, LOAD/SHIFT, TX Q0, and RX Q0.

Output Light

×8

Role: Displays receiver outputs Q0 through Q7.

Applications and Design Context

Serial datapath fundamentals. PISO and SIPO stages form the data-conversion core of many synchronous serial interfaces.

Loopback verification. A known alternating pattern such as 0xAA is useful for checking bit order and edge count.

Scan chains. Serial shifting can transport a parallel test state through a narrow connection.

Interface education. The deliberately minimal circuit separates data shifting from framing, synchronization, and error detection.

Frequently Asked Questions

Which byte does this circuit transmit?

Four fixed logic sources drive the transmit register as Q7..Q0 = 10101010. The user cannot select a different byte with data switches in this production circuit.

How is the transmitter changed from load to shift mode?

Set LOAD/SHIFT high for a rising edge so the PISO stage parallel-loads the transmit-register outputs. Then set it low; subsequent rising edges shift data out through SO.

Which bit is transmitted first?

Both shift registers have DIR = 0. SO therefore reflects the transmitter's Q0, and each receiver edge places the serial bit in Q7. The fixed 0xAA byte is sent in the chronological order 0,1,0,1,0,1,0,1.

Is this a complete UART or SPI link?

No. The circuit has a shared clock but no start bit, stop bit, parity, chip-select, ready strobe, or clock-recovery logic. It demonstrates only the core parallel-load/serial-shift/parallel-observe path.

Which signals are observable?

Channels 1–5 show CLK, serial line, LOAD/SHIFT, transmit-register Q0, and receiver Q0. Channels 6–8 are unconnected. Eight lights show receiver Q0..Q7.