4-Bit PISO Shift Register Simulator

Fig. 1 — 4-Bit PISO Shift RegisterInteractive simulation

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A parallel-in, serial-out (PISO) register captures a 4-bit word at once and then transmits it over one data line, one bit per clock.

What You'll Learn

Capture D3..D0 simultaneously in parallel-load mode.
Switch to right-shift mode and serialize the stored word through Q0.
Predict both the internal Q3..Q0 state and Serial Out after each edge.
Distinguish sampling the outgoing bit from updating the shift-register state.
Relate PISO operation to serial transmission, scan chains, and pin-count reduction.

How It Works

The integrated 4-bit shift-register component has serial input, clock, direction, shift/load, and D0..D3 inputs. In this circuit, both Serial In and Direction are tied to logic LOW. Direction = 0 selects a right shift toward Q0, so Serial Out is Q0 and each shift inserts 0 at Q3.

With Load = 1, a rising clock edge copies D3..D0 into Q3..Q0 simultaneously. Set Load = 0 before subsequent rising edges. The next-state relation is Q0(next) = Q1, Q1(next) = Q2, Q2(next) = Q3, and Q3(next) = 0. A receiver should sample Serial Out immediately before each shift edge; for loaded word 1011₂, the Q0-first serialized sequence is 1, 1, 0, 1.

The four parallel output lights make the internal state visible while the fifth light exposes Serial Out. After four right-shift edges, the original word has completely left the register and the fixed zero serial input has filled every stage. In a practical transmitter, a bit counter and framing control would indicate when the four-bit transfer begins and ends.

Boolean Expression

Load = 1:\quad (Q_3^{+},Q_2^{+},Q_1^{+},Q_0^{+})=(D_3,D_2,D_1,D_0)

When Load is HIGH, the next rising edge captures the four parallel D inputs without reordering.

Load = 0:\quad (Q_3^{+},Q_2^{+},Q_1^{+},Q_0^{+})=(0,Q_3,Q_2,Q_1)

When Load is LOW, Direction = 0, and Serial In = 0, the register shifts toward Q0 and inserts zero at Q3.

SO = Q_0

For the fixed right-shift direction, the serial output is the current least-significant stage Q0.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
Clock=0 -> 1D3..D0=1011Initial state=reload templateLoad=1
Expected:Q3..Q0 = 1011 and Serial Out = 1
What you'll see:The load edge captures the full word. Because Q0 is the least-significant loaded bit, Serial Out is already the first bit to transmit.
2
Action=sample Serial Out, then apply first rising edgeLoad=0
Expected:First sampled bit = 1; after the edge Q3..Q0 = 0101 and Serial Out = 1
What you'll see:Sample Q0 before the edge, then shift. Q1 moves into Q0, so Serial Out becomes the second original bit.
3
Action=sample Serial Out, then apply second rising edgeLoad=0
Expected:Second sampled bit = 1; after the edge Q3..Q0 = 0010 and Serial Out = 0
What you'll see:Sampling and shifting again emits the original D1 bit and exposes the original D2 bit at Q0.
4
Action=sample before each of the third and fourth rising edgesLoad=0
Expected:Remaining sampled bits = 0, 1; after four shift edges Q3..Q0 = 0000
What you'll see:The third and fourth samples complete the Q0-first stream 1, 1, 0, 1. Fixed zero input then leaves the register at 0000.

Components Used

4-Bit Shift Register

×1

Role: The 4-bit storage element performs synchronous parallel load and fixed-direction serial shifting.

Logic-LOW Constant

×1

Role: One LOW source fixes Serial In and Direction at zero.

Input Switch

×6

Role: Four switches define D3..D0; two more control Clock and Load/Shift.

Output Light

×5

Role: Four lights expose Q3..Q0 and one displays the current Serial Out bit.

Applications and Design Context

Serial transmitters. UART-, SPI-, and custom synchronous interfaces use shift-register logic to present a parallel word one bit at a time, although protocol-specific framing and bit order vary.

I/O pin reduction. Parallel state can be serialized across a small number of wires between devices or boards.

Scan and test chains. Internal register state is captured in parallel and shifted out for manufacturing test and diagnosis.

Sensor and converter interfaces. Parallel conversion results may be shifted to a controller through a serial output.

Cascaded output devices. Similar load-and-shift structures move display or actuator patterns through daisy-chained hardware.

Frequently Asked Questions

Which bit is transmitted first?

Q0 is transmitted first because Direction is tied LOW and Serial Out selects Q0 for a right shift. For loaded D3..D0 = 1011, the sampled stream is D0, D1, D2, D3 = 1, 1, 0, 1.

When should the receiver sample Serial Out?

For this walkthrough, read the current Q0 value immediately before the rising edge that shifts it out. A complete hardware protocol defines an exact sampling edge, launch edge, and timing margin for both endpoints.

What happens if Load remains HIGH?

Every rising edge reloads D3..D0 instead of shifting. Set Load LOW after the capture edge to begin serialization.

Why are Serial In and Direction tied to zero?

The fixed inputs make this a deterministic PISO example: it always shifts toward Q0 and fills vacated Q3 positions with zero. A universal shift register can expose both controls for bidirectional shifting and chained serial input.

How does PISO differ from SIPO?

PISO converts one parallel word into a serial stream. SIPO performs the inverse operation by receiving bits serially and exposing the assembled word on parallel outputs.