1-to-2 Demultiplexer Circuit Simulator

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What You'll Learn

Route a single data input to one of two outputs based on the select bit.
Read the DEMUX truth table — exactly one output is non-zero at a time.
Distinguish DEMUX (one input, many outputs) from MUX (many inputs, one output).
Recognize that DEMUX with D=1 acts as a 1-of-N decoder.
Apply DEMUX in TDM, write-back routing, and chip-select generation.

How It Works

A demultiplexer (DEMUX) is the inverse of a multiplexer: one data input, multiple outputs, and a select line that picks which output the input is routed to. The 1-to-2 DEMUX is the simplest case: one data input D, one select S, two outputs Y0 and Y1.

When S = 0, Y0 = D and Y1 = 0 (D goes to output 0; output 1 is silenced). When S = 1, Y1 = D and Y0 = 0 (D goes to output 1; output 0 is silenced).

Boolean expressions: Y0 = ¬S · D, Y1 = S · D. Each output is the AND of D with one select-code.

DEMUXes are essential when you have a serial data stream that needs to be distributed to multiple destinations — one DEMUX, one source, many sinks. Combined with a MUX at the receiving side, you get time-division multiplexing — sharing a single channel among multiple senders/receivers by interleaving their data based on a select clock.

A 1-to-N DEMUX is also functionally identical to a decoder with enable: with the data input held high, only the selected output goes high — exactly what a decoder does.

Truth Table

Two outputs, one always 0 (the unselected one). Showing the four (S, D) combinations.

Inputs		Output
S	D	Y0	Y1
0	0	0	0	S=0, D=0 — Y0 active but D is 0
0	1	1	0	S=0, D=1 — D routed to Y0
1	0	0	0	S=1, D=0 — Y1 active but D is 0
1	1	0	1	S=1, D=1 — D routed to Y1

Boolean Expression

Y_0 = \overline{S} \cdot D

Output 0 is high only when S=0 AND D=1.

Y_1 = S \cdot D

Output 1 is high only when S=1 AND D=1.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

S = 0 D = 0

Expected: Y0=0, Y1=0

What you'll see: Default state — no data flowing means both outputs stay low regardless of select.
2

S = 0 D = 1

Expected: Y0=1, Y1=0

What you'll see: Select=0 routes D=1 to Y0. Y1 stays inactive.
3

S = 1 D = 1

Expected: Y0=0, Y1=1

What you'll see: Flip the select — now D=1 goes to Y1 instead. Y0 silences.
4

S = 1 D = 0

Expected: Y0=0, Y1=0

What you'll see: S=1 selects Y1 but D=0, so the active output stays low. Both outputs low — DEMUX correctly silences Y0 and routes the inactive D to Y1.

Components Used

Input Switch

×2

Demultiplexer (1-to-2)

×1

Output Light

×2

Real-World Applications

Memory write-back routing. Write data flows from CPU through a DEMUX that routes it to the correct memory bank or register based on the address.

TDM (time-division multiplexing). A single high-bandwidth channel carries multiple low-bandwidth streams; on the receiver side a DEMUX clocked in sync with the sender splits the streams back out.

1-of-N enable signal generation. Driving a DEMUX with a constant 1 makes it a one-hot decoder — exactly one output high, all others low. Used for chip-select fan-out and one-hot state encoding.

Channel routing in switches. Network switches use DEMUXes to direct an incoming packet to the correct outgoing port based on routing-table lookup.

Test mode signal routing. Scan-out chains in DFT (design-for-test) use DEMUXes to direct test data to the appropriate scan path.

Frequently Asked Questions

Why is DEMUX called the inverse of MUX?

MUX takes many inputs and produces one output (selecting which input to route). DEMUX takes one input and produces many outputs (selecting which output gets the input). They're functional inverses, often paired in TDM systems.

What's the difference between a DEMUX and a decoder?

Strict decoders have only the select bits as input — no data. With D held high, a DEMUX becomes a decoder: exactly one output asserts. A DEMUX is more general because it can also pass arbitrary D values through the selected output.

Can I build a 1-to-4 DEMUX from 1-to-2 DEMUXes?

Yes — it's a tree. One 1-to-2 splits the input via the high select bit; each output feeds another 1-to-2 split via the low select bit. Three 1-to-2 DEMUXes total.

Why do I need a DEMUX if I can just AND each output with a select decode?

Functionally, a DEMUX *is* an AND of D with each select decode. The component view just packages the pattern for clarity. In standard cell libraries, DEMUXes are sometimes optimised below the AND-tree decomposition, but logically they're equivalent.

What's the propagation delay through a DEMUX?

About 1 to 2 gate delays, depending on width. A 1-to-2 has ~1 gate delay (a single AND); wider DEMUXes have a small decoder tree adding ~log₂N delay.