1-to-2 Demultiplexer
One select bit routes data input D to Y0 or Y1 while driving the unselected output LOW. When D is LOW, both visible outputs are LOW.
What You'll Learn
- Route a single data input to one of two outputs based on the select bit.
- Read the DEMUX truth table and recognize that at most one output is non-zero at a time.
- Distinguish DEMUX (one input, many outputs) from MUX (many inputs, one output).
- Recognize that DEMUX with D=1 acts as a 1-of-N decoder.
- Apply DEMUX in TDM, write-back routing, and chip-select generation.
How It Works
A demultiplexer (DEMUX) is the routing counterpart of a multiplexer: it has one data input, multiple outputs, and a select input that determines which output receives the data value. The 1-to-2 DEMUX is the simplest case, with data D, select S, and outputs Y0 and Y1.
When S = 0, Y0 = D and Y1 = 0. When S = 1, Y1 = D and Y0 = 0. Thus Y0 = ¬S · D and Y1 = S · D. Each output is the conjunction of D with its select-code minterm.
A DEMUX can distribute a scheduled data stream or, more commonly in digital control, route an enable or write strobe to one destination. A receiving MUX may recombine scheduled channels only when both endpoints use coordinated selection; the pair is not intrinsically lossless or self-synchronizing.
With D held HIGH, the outputs form a one-hot decode of S. In that operating mode a 1-to-N DEMUX has the same Boolean output function as an N-output decoder with an asserted enable input.
Truth Table
Two outputs, one always 0 (the unselected one). Showing the four (S, D) combinations.
| Inputs | Output | |||
|---|---|---|---|---|
| S | D | Y0 | Y1 | |
| 0 | 0 | 0 | 0 | S=0, D=0 — Y0 active but D is 0 |
| 0 | 1 | 1 | 0 | S=0, D=1 — D routed to Y0 |
| 1 | 0 | 0 | 0 | S=1, D=0 — Y1 active but D is 0 |
| 1 | 1 | 0 | 1 | S=1, D=1 — D routed to Y1 |
Boolean Expression
Output 0 is high only when S=0 AND D=1.
Output 1 is high only when S=1 AND D=1.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1D=0S=0Expected:
Y0=0, Y1=0What you'll see:Default state — no data flowing means both outputs stay low regardless of select. - 2D=1S=0Expected:
Y0=1, Y1=0What you'll see:Select=0 routes D=1 to Y0. Y1 stays inactive. - 3D=1S=1Expected:
Y0=0, Y1=1What you'll see:Flip the select — now D=1 goes to Y1 instead. Y0 silences. - 4D=0S=1Expected:
Y0=0, Y1=0What you'll see:S=1 selects Y1 but D=0, so the active output stays low. Both outputs low — DEMUX correctly silences Y0 and routes the inactive D to Y1.
Components Used
Applications and Design Context
Memory write-back routing. Write data flows from CPU through a DEMUX that routes it to the correct memory bank or register based on the address.
TDM (time-division multiplexing). A single high-bandwidth channel carries multiple low-bandwidth streams; on the receiver side a DEMUX clocked in sync with the sender splits the streams back out.
1-of-N enable signal generation. Driving a DEMUX with a constant 1 makes it a one-hot decoder — exactly one output high, all others low. Used for chip-select fan-out and one-hot state encoding.
Channel routing in switches. Network switches use DEMUXes to direct an incoming packet to the correct outgoing port based on routing-table lookup.
Test mode signal routing. Scan-out chains in DFT (design-for-test) use DEMUXes to direct test data to the appropriate scan path.
Frequently Asked Questions
In what sense is a DEMUX the counterpart of a MUX?
A MUX selects one of many inputs for one output; a DEMUX routes one input toward one of many outputs. They are complementary routing functions, although neither generally reconstructs information discarded by the other. Systems often pair them when both ends share the same channel schedule.
What's the difference between a DEMUX and a decoder?
Strict decoders have only the select bits as input — no data. With D held high, a DEMUX becomes a decoder: exactly one output asserts. A DEMUX is more general because it can also pass arbitrary D values through the selected output.
Can I build a 1-to-4 DEMUX from 1-to-2 DEMUXes?
Yes — it's a tree. One 1-to-2 splits the input via the high select bit; each output feeds another 1-to-2 split via the low select bit. Three 1-to-2 DEMUXes total.
Why do I need a DEMUX if I can just AND each output with a select decode?
Functionally, a DEMUX *is* an AND of D with each select decode. The component view just packages the pattern for clarity. In standard cell libraries, DEMUXes are sometimes optimized below the AND-tree decomposition, but logically they're equivalent.
Can this template predict a physical DEMUX delay?
This behavioral component does not model a particular logic family or physical delay. A gate-level realization requires select decoding and output gating; its propagation delay depends on the chosen topology, cell library, fan-out, routing, voltage, and load.