Two-Half-Adder Topology (Cin = 0)
Two half adders and an OR gate resemble a full-adder decomposition, but the second half adder receives a fixed logic 0 instead of a controllable Cin. The external two-input function is therefore a half adder.
What You'll Learn
- Trace a two-half-adder plus OR topology at the component level.
- Identify the CONSTANT_ZERO connection as a fixed Cin of 0.
- Derive why the second carry term is always 0 in this circuit.
- Verify that the visible function reduces to a half-adder truth table.
- Explain the wiring change required to expose a controllable Cin.
How It Works
The production circuit contains two input switches, two HALF_ADDER components, one OR gate, one CONSTANT_ZERO source, and three digit displays. Its wiring resembles the standard two-half-adder decomposition of a full adder, with one critical limitation: the second half adder's second input is fixed at logic 0.
The signal path is: 1. The first half adder computes P = A ⊕ B and C1 = A·B. 2. The second half adder computes Sum = P ⊕ 0 = P and C2 = P·0 = 0. 3. The OR gate computes Cout = C1 + C2 = A·B.
Consequently, the external function has only the two controllable inputs A and B. It produces the same Sum and Cout values as a half adder; it does not expose a switchable Cin. A general full adder would replace the constant-low source with a third input.
The two operand displays mirror A and B. The result display receives Sum on bit 0 and Cout on bit 1 and therefore shows the complete result as decimal 0, 1, or 2.
Truth Table
Only A and B are controllable. Sum and Cout feed bits 0 and 1 of the result display; Cin is physically fixed at 0.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| A | B | Sum | Cout | Result display | |
| 0 | 0 | 0 | 0 | 0 | 0 + 0 + Cin(0) = 00; result display reads 0 |
| 0 | 1 | 1 | 0 | 1 | 0 + 1 + Cin(0) = 01; result display reads 1 |
| 1 | 0 | 1 | 0 | 1 | 1 + 0 + Cin(0) = 01; result display reads 1 |
| 1 | 1 | 0 | 1 | 2 | 1 + 1 + Cin(0) = 10; result display reads 2 |
Boolean Expression
The first half adder produces intermediate sum P and carry C1 from A and B.
The second half adder receives P and a physical CONSTANT_ZERO source, so its sum remains P and its carry C2 is always 0.
The OR gate combines the two carry terms. With Cin fixed at 0, Cout reduces to A·B.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A=0B=0Expected:
Sum = 0, Cout = 0, result display = 0What you'll see:Both inputs low produce Sum = 0 and Cout = 0. - 2A=0B=1Expected:
Sum = 1, Cout = 0, result display = 1What you'll see:With only B high, the first half adder sets P; the second passes P through because its other input is 0. - 3A=1B=0Expected:
Sum = 1, Cout = 0, result display = 1What you'll see:With only A high, the result remains 1, confirming the symmetry of the two operand inputs. - 4A=1B=1Expected:
Sum = 0, Cout = 1, result display = 2What you'll see:With A and B high, the first carry C1 sets Cout. The second carry C2 remains 0 because Cin is fixed low.
Components Used
Applications and Design Context
Least-significant adder stage. The first stage of an unsigned ripple-carry adder commonly receives a fixed carry-in of 0.
Hierarchical arithmetic education. The visible HALF_ADDER blocks and OR gate show the standard structural decomposition before Cin is made controllable.
Constant propagation in synthesis. A synthesis tool can simplify logic driven by a constant, reducing this topology to its effective XOR-and-AND behavior.
Interface verification. Comparing the drawn topology with its actual external inputs prevents a packaged block name from being mistaken for behavior that the wiring does not provide.
Frequently Asked Questions
Is this a complete, controllable full adder?
A general full adder can be decomposed into two half adders and an OR gate. In this production circuit, however, the second half adder's second data input—which serves as Cin in that decomposition—is permanently connected to CONSTANT_ZERO. The topology is visible, but its current external behavior is the same as a half adder.
How can the circuit be converted into a general full adder?
Replace the CONSTANT_ZERO connection with a third input switch named Cin. The first half adder would still add A and B; the second would add Cin to the intermediate sum; the OR gate would combine both carry terms.
Why can the second half adder never generate a carry?
C2 is the AND of the intermediate sum P and the second half adder's other input. That other input is fixed at 0, so C2 = P·0 = 0 for every A,B combination.
What do the three digit displays show?
The A and B displays mirror the two switches. The result display receives Sum on bit 0 and Cout on bit 1, so it reads 0, 1, or 2. There are no separate output lights in the production circuit.
When is tying Cin to 0 appropriate?
A fixed Cin of 0 is appropriate for an isolated one-bit addition or for the least-significant stage of an unsigned adder. Higher stages require a carry input connected to the preceding stage's carry-out.