1-Bit Half Adder
An XOR gate produces Sum and an AND gate produces Carry for two one-bit operands. Three digit displays show the operands and the combined two-bit result.
What You'll Learn
- Compute the Sum and Carry outputs for two one-bit operands.
- Relate the XOR path to Sum and the AND path to Carry.
- Read the A, B, and combined result digit displays correctly.
- Explain why a half adder cannot accept an incoming carry.
- Use the half-adder function at a bit position that has no carry-in.
How It Works
A half adder adds two one-bit operands, A and B. The circuit exposes the implementation directly: one XOR gate produces Sum, and one AND gate produces Carry.
- Sum = A ⊕ B: high when exactly one input is high. - Carry = A · B: high only when both inputs are high.
The four input cases are 0 + 0 = 00, 0 + 1 = 01, 1 + 0 = 01, and 1 + 1 = 10. In the last case, the low sum bit returns to 0 while Carry becomes the high bit of the two-bit result.
The production circuit contains three digit displays. Two displays mirror the individual A and B switches. The result display receives Sum on bit 0 and Carry on bit 1, so it shows the decimal values 0, 1, or 2. No separate output light is present.
A half adder has no carry-in pin. For a multi-bit ripple adder, the least-significant position may use this circuit, while each higher position needs a full-adder function that also accepts the preceding carry.
Truth Table
The two outputs form a two-bit result ordered as Carry, Sum; the result display receives Sum on bit 0 and Carry on bit 1.
| Inputs | Output | |||
|---|---|---|---|---|
| A | B | Sum | Carry | |
| 0 | 0 | 0 | 0 | 0 + 0 = 00 (decimal 0) |
| 0 | 1 | 1 | 0 | 0 + 1 = 01 (decimal 1) |
| 1 | 0 | 1 | 0 | 1 + 0 = 01 (decimal 1) |
| 1 | 1 | 0 | 1 | 1 + 1 = 10 (decimal 2) |
Boolean Expression
The least-significant result bit is the XOR of A and B.
The carry bit is the AND of A and B, so it is high only when both operands are 1.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A=0B=0Expected:
Sum = 0, Carry = 0, result display = 0What you'll see:Both input displays and the result display read 0. - 2A=1B=0Expected:
Sum = 1, Carry = 0, result display = 1What you'll see:With only A high, XOR sets Sum while AND leaves Carry low; the result display reads 1. - 3A=0B=1Expected:
Sum = 1, Carry = 0, result display = 1What you'll see:With only B high, the result is again 1, confirming that both XOR and AND are commutative. - 4A=1B=1Expected:
Sum = 0, Carry = 1, result display = 2What you'll see:With A and B high, XOR clears Sum and AND asserts Carry; the result display reads binary 10, or decimal 2.
Components Used
Applications and Design Context
Least-significant adder stage. When a ripple-carry adder has a fixed Cin of 0, its lowest stage can use a half-adder function.
Increment and carry generation. Adding an increment bit to a stored bit uses XOR for the new value and AND for the carry into the next position.
Multiplier reduction networks. Half adders combine two partial-product bits in columns that have no third input.
Arithmetic education and verification. The explicit XOR and AND paths make the origin of the two result bits directly observable.
Logic synthesis. Synthesis tools may map this Boolean function to a dedicated half-adder cell or to equivalent gates, depending on the target library.
Frequently Asked Questions
Why is it called a half adder?
It has no carry-in input from a lower bit position. A full adder accepts A, B, and Cin. A half adder is sufficient whenever no incoming carry is required, including the least-significant position of this simple ripple-carry pattern.
Can a multi-bit adder use only one half adder per bit?
Not by simply chaining one half adder per bit, because every position above bit 0 must also add the carry from the preceding position. A full-adder stage can be constructed from two half adders and an OR gate, but that additional carry path is essential.
How is this half adder implemented?
The visible gate-level implementation uses one XOR gate for Sum and one AND gate for Carry. A physical transistor count and delay depend on the selected cell library and circuit topology; this simulator verifies the logical function rather than a particular CMOS implementation.
How does a half adder relate to a full adder?
A standard full-adder decomposition uses two half adders and an OR gate. The first half adder combines A and B; the second combines that intermediate sum with Cin; the two carry terms are ORed to produce Cout.
Why is XOR alone not a complete one-bit adder?
XOR alone produces the low sum bit but discards the carry. The AND output records the 1 + 1 case as Carry = 1. Together, Sum and Carry encode the complete two-bit result from 0 through 2.