Single-Bit Tri-State Buffer
Basic tri-state buffer with enable control. Learn about high-impedance state and shared bus concepts in digital systems.
What You'll Learn
- Identify the three states of a tri-state buffer's output: 0, 1, and Z (high impedance).
- Distinguish high-Z from logic 0 — Z is disconnected; 0 actively drives low.
- Explain why tri-state buffers enable shared buses.
- Read the tri-state truth table including the Z row when enable is low.
- Recognise the schematic symbol: a buffer triangle with a perpendicular enable pin.
How It Works
A tri-state buffer is a buffer with a third possible output state: Z (high impedance). When the enable input is asserted (EN = 1), it behaves exactly like a normal buffer — output follows input. When enable is deasserted (EN = 0), the output disconnects: it neither drives 0 nor 1, so any other driver on the wire takes over.
This circuit isolates that single behaviour into one component: one data input A, one enable input EN, one output Y. With two binary inputs there are four combinations, but only two distinct output behaviours: Y = A (when EN = 1) and Y = Z (when EN = 0).
The high-impedance state is what makes shared buses possible. Without tri-state, every wire would need its own dedicated driver — impractical for any system where many devices need to send data over the same lines. With tri-state, devices share a bus and arbitrate access via their enable lines.
In schematics, tri-state buffers look like a regular buffer (triangle) with an extra control pin entering perpendicular to the data path. In silicon, they're implemented as a buffer whose output transistors can both be turned off simultaneously, leaving the pin floating.
Truth Table
Two inputs (A, EN), one output. EN = 1 means output follows A; EN = 0 means output is high-Z (disconnected).
| Inputs | Output | ||
|---|---|---|---|
| A | EN | Y | |
| 0 | 0 | 0 | Disabled — Y floats to Z (often pulled to 0 by default) |
| 1 | 0 | 0 | Disabled — Y floats regardless of A |
| 0 | 1 | 0 | Enabled — Y = A |
| 1 | 1 | 1 | Enabled — Y = A |
Boolean Expression
Tri-state can't be expressed as a pure Boolean function — Z isn't a logic value. It requires a state-aware description.
Active behaviour: pass-through buffer when enabled.
Try It Step-by-Step
Set the inputs in the embed above, then read what should happen and confirm.
- 1A = 0 EN = 1Expected:
Y = 0What you'll see: Buffer enabled, A is 0, output is 0. Acts as a regular buffer. - 2A = 1 EN = 1Expected:
Y = 1What you'll see: Buffer enabled, A is 1, output is 1. Pass-through behaviour. - 3A = 1 EN = 0Expected:
Y = Z (high-Z)What you'll see: Buffer disabled — output disconnects. Notice that the output light is dark, but in a real circuit some other driver could now take over the wire. The simulator usually shows Z as 0 (or a special pattern). - 4A = 0 EN = 0Expected:
Y = Z (high-Z)What you'll see: Same disconnected state. The output is independent of A when EN = 0 — that's the whole point of tri-state.
Components Used
Real-World Applications
Memory data lines. Each RAM and ROM chip drives the data bus through tri-state buffers gated by chip-select. Only the selected chip drives; the others float, leaving the bus to it.
Register-file output multiplexing. Inside a CPU, all registers connect to a shared internal read bus through tri-state buffers. The instruction decoder enables exactly one register's tri-state at a time.
Bidirectional I/O pins. A single chip pin can be input or output by combining a tri-state output buffer with an input buffer. When the tri-state is disabled, the pin reads as input; when enabled, it drives.
Bus arbitration in multi-master systems. PCI, AMBA AHB, and similar protocols use tri-state to allow multiple bus masters to take turns driving the data lines.
Test and debug isolation. During chip test, internal signals are routed to test pins via tri-state buffers that disable normal operation and enable test mode.