1-to-8 Demultiplexer
A 3-bit select code routes one data input to one of eight outputs. With D HIGH the output vector is one-hot; with D LOW all eight outputs are LOW.
What You'll Learn
- Use a 3-bit select to route one input to one of 8 outputs.
- Read the 1-to-8 DEMUX truth table — only one output equals D at a time.
- Recognize that a 1-to-8 DEMUX with D=1 is a 3-to-8 decoder.
- Build 1-to-8 from a tree of 1-to-2 or 1-to-4 stages.
- Apply for 8-bank memory routing and 8-way chip-select fan-out.
How It Works
A 1-to-8 demultiplexer routes one data input D to one of eight outputs Y0–Y7 according to the 3-bit select code S2S1S0. Three select bits encode 2³ = 8 destinations.
For each output Yi, Yi = mi(S2,S1,S0) · D, where mi is the unique minterm for index i. Exactly one output is selected; it reproduces D, while the other seven outputs are driven LOW. If D is LOW, all eight outputs are LOW even though one path remains selected.
Holding D HIGH makes the output vector one-hot, so the component behaves as a 3-to-8 decoder with an asserted enable. Driving D with a write-enable or strobe instead routes that control event to one addressed memory bank, register, or peripheral.
Gate-level implementations may use shared decoding, AND/OR structures, transmission gates, or library-specific cells. The logical cost grows with the number of output paths, but physical area and timing cannot be inferred from the packaged symbol alone.
Truth Table
Showing all 8 select codes with D=1 to see which output activates each time.
| Inputs | Output | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| S2 | S1 | S0 | D | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Y0 = D |
| 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Y1 = D |
| 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Y2 = D |
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Y3 = D |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Y4 = D |
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Y5 = D |
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Y6 = D |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Y7 = D — last output |
Boolean Expression
Where m_i is the i-th 3-variable minterm. Each output ANDs D with its unique select-code minterm.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1D=1S0=0S1=0S2=0Expected:
Y0=1, others=0What you'll see:Select 000 → Y0 receives D. All other outputs dark. - 2D=1S0=1S1=1S2=1Expected:
Y7=1, others=0What you'll see:Select 111 → Y7. The active output walked all the way to the top. - 3D=0S0=0S1=1S2=0Expected:
All outputs = 0What you'll see:Select 010 picks Y2, but D=0 so Y2 stays low. DEMUX's job is to gate D — when D is 0 nothing activates. - 4D=1S0=1S1=0S2=1Expected:
Y5=1, others=0What you'll see:Select 101 = 5 in binary → Y5 lights. Try to enumerate all 8 select codes mentally.
Components Used
Applications and Design Context
8-bank memory write routing. A 3-bit bank selector and a 1-to-8 DEMUX gates the write-enable to exactly one bank.
3-bit chip select. A microcontroller with up to 8 peripherals uses 3 address bits and a 1-to-8 DEMUX to assert exactly one chip-select line.
Octal channel switching. Audio, video, and instrumentation systems route a single source signal to one of 8 channels via DEMUXes.
Network port enable. A 4-port switch with 8-port expansion uses a 1-to-8 DEMUX in the management plane to route control commands to specific ports.
Test scan output routing. DFT scan-out chains use small DEMUXes to direct scan data to one of several scan paths during test.
Frequently Asked Questions
How is a 1-to-8 DEMUX different from a 3-to-8 decoder?
Decoder asserts exactly one output high (no data input). DEMUX gates a data input D through to one selected output. With D held high, they're identical. With D varying, DEMUX passes D's value to the selected output; decoder doesn't have that capability.
Can I build a 1-to-8 from two 1-to-4 DEMUXes?
Yes. Feed D to a 1-to-2 DEMUX selected by S2, and connect its two outputs to the data inputs of two 1-to-4 DEMUXes; both 1-to-4 units use S1 and S0. This requires one 1-to-2 plus two 1-to-4 DEMUXes. If the 1-to-4 devices have enable inputs, an alternative is to drive both with D and use S2 and ¬S2 to enable exactly one.
Can this template predict the worst-case physical delay?
The behavioral DEMUX does not model a specific physical implementation. A gate-level design must decode three select bits and gate D onto eight outputs, but its delay depends on decomposition, cell library, fan-out, routing, voltage, and load.
Are wide DEMUXes practical?
Yes — 1-to-32 and 1-to-64 DEMUXes appear in memory subsystems and crossbar switches. Their cost grows linearly in outputs (one AND each) plus the decoder, so they scale efficiently.
How does this relate to one-hot state machines?
In a valid one-hot state, exactly one of N state flip-flops is set. Some transitions can be viewed as DEMUX-like steering of an active-state contribution toward one of several next-state bits, but a general next-state network may combine multiple current-state bits and inputs and is not simply a DEMUX. Moore-style state outputs can still provide a one-of-many action pattern.