1-to-8 Demultiplexer Circuit Simulator

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What You'll Learn

Use a 3-bit select to route one input to one of 8 outputs.
Read the 1-to-8 DEMUX truth table — only one output equals D at a time.
Recognise that a 1-to-8 DEMUX with D=1 is a 3-to-8 decoder.
Build 1-to-8 from a tree of 1-to-2 or 1-to-4 stages.
Apply for 8-bank memory routing and 8-way chip-select fan-out.

How It Works

A 1-to-8 demultiplexer routes one data input to one of eight outputs (Y0–Y7), based on a 3-bit select code (S2 S1 S0). Three select bits address 2³ = 8 outputs.

For each output Yi, Yi = (matching minterm of S2S1S0) · D. Only one output reflects D; the other seven are 0.

A 1-to-8 DEMUX is the natural building block for 8-way routing: 8 memory banks, 8 peripheral chip-selects, 8 channels of TDM. With D held high it becomes a 3-to-8 decoder.

Gate-count comparison: a 1-to-8 DEMUX is about 8 ANDs plus a 3-to-8 select decoder (8 minterms × 3 ANDs each, with the 3 inverters shared). Total ~24 transistor-equivalent gates. Larger than a 1-to-2 (one AND), smaller than a 32-row mux.

The key practical insight: as N grows, DEMUX cost grows linearly (one output AND per output) plus the decoder's logarithmic depth. They scale gracefully.

Truth Table

Showing all 8 select codes with D=1 to see which output activates each time.

Inputs			Output
S2	S1	S0	Active Output
0	0	0	1	Y0 = D
0	0	1	1	Y1 = D
0	1	0	1	Y2 = D
0	1	1	1	Y3 = D
1	0	0	1	Y4 = D
1	0	1	1	Y5 = D
1	1	0	1	Y6 = D
1	1	1	1	Y7 = D — last output

Boolean Expression

Y_i = m_i(S_2, S_1, S_0) \cdot D

Where m_i is the i-th 3-variable minterm. Each output ANDs D with its unique select-code minterm.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

S2 = 0 S1 = 0 S0 = 0 D = 1

Expected: Y0=1, others=0

What you'll see: Select 000 → Y0 receives D. All other outputs dark.
2

S2 = 1 S1 = 1 S0 = 1 D = 1

Expected: Y7=1, others=0

What you'll see: Select 111 → Y7. The active output walked all the way to the top.
3

S2 = 0 S1 = 1 S0 = 0 D = 0

Expected: All outputs = 0

What you'll see: Select 010 picks Y2, but D=0 so Y2 stays low. DEMUX's job is to gate D — when D is 0 nothing activates.
4

S2 = 1 S1 = 0 S0 = 1 D = 1

Expected: Y5=1, others=0

What you'll see: Select 101 = 5 in binary → Y5 lights. Try to enumerate all 8 select codes mentally.

Components Used

Input Switch

×4

Demultiplexer (1-to-8)

×1

Output Light

×8

Real-World Applications

8-bank memory write routing. A 3-bit bank selector and a 1-to-8 DEMUX gates the write-enable to exactly one bank.

3-bit chip select. A microcontroller with up to 8 peripherals uses 3 address bits and a 1-to-8 DEMUX to assert exactly one chip-select line.

Octal channel switching. Audio, video, and instrumentation systems route a single source signal to one of 8 channels via DEMUXes.

Network port enable. A 4-port switch with 8-port expansion uses a 1-to-8 DEMUX in the management plane to route control commands to specific ports.

Test scan output routing. DFT scan-out chains use small DEMUXes to direct scan data to one of several scan paths during test.

Frequently Asked Questions

How is a 1-to-8 DEMUX different from a 3-to-8 decoder?

Decoder asserts exactly one output high (no data input). DEMUX gates a data input D through to one selected output. With D held high, they're identical. With D varying, DEMUX passes D's value to the selected output; decoder doesn't have that capability.

Can I build a 1-to-8 from two 1-to-4 DEMUXes?

Yes. Use the high select bit S2 to choose between two 1-to-4 DEMUXes (each with S1, S0 as their select). The two DEMUXes share data input D; the high select gates which sub-DEMUX is active. Total: 2 × 1-to-4 + the steering AND on D.

What's the worst-case delay through a 1-to-8 DEMUX?

Roughly 3 gate delays: select-bit inverters, then a 3-input AND for the minterm, then a 2-input AND with D. Modern CMOS resolves this in well under a clock cycle for typical clock speeds.

Are wide DEMUXes practical?

Yes — 1-to-32 and 1-to-64 DEMUXes appear in memory subsystems and crossbar switches. Their cost grows linearly in outputs (one AND each) plus the decoder, so they scale efficiently.

How does this relate to one-hot state machines?

A one-hot FSM has exactly one of N flip-flops set at a time. The next-state logic feeding the DFFs is essentially a DEMUX whose select is derived from the current state and inputs. Each state's output strobes a different action — same fan-out pattern.