1-to-4 Demultiplexer
A 2-bit select code routes one data input to one of four outputs. The selected output follows D, and the other three outputs remain LOW.
What You'll Learn
- Use a 2-bit select to route one input to one of 4 outputs.
- Read the 1-to-4 DEMUX behavior table — only one output is active at a time.
- Derive the per-output Boolean expressions as AND of D with select-decode.
- Recognize the equivalence: DEMUX with D=1 is a 2-to-4 decoder.
- Apply 1-to-4 DEMUXes for memory-bank routing and chip-select fan-out.
How It Works
A 1-to-4 demultiplexer routes one data input D to one of four outputs (Y0–Y3), based on a 2-bit select code (S1, S0). The selected output equals D; the other three are 0.
Mapping: - S1S0 = 00 → Y0 = D, others = 0 - S1S0 = 01 → Y1 = D, others = 0 - S1S0 = 10 → Y2 = D, others = 0 - S1S0 = 11 → Y3 = D, others = 0
Boolean: each output ANDs D with the matching minterm of the select bits. Y0 = ¬S1·¬S0·D, Y1 = ¬S1·S0·D, Y2 = S1·¬S0·D, Y3 = S1·S0·D.
With D held high, the DEMUX becomes a 2-to-4 decoder — useful for chip-select and address decoding. With D varying, it's a router for distributing one signal to one of four destinations based on select.
Truth Table
The first four rows show D=1 with each of the four select codes. With D=0, all outputs are 0.
| Inputs | Output | ||||||
|---|---|---|---|---|---|---|---|
| S1 | S0 | D | Y0 | Y1 | Y2 | Y3 | |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | Select 00 → Y0 receives D |
| 0 | 1 | 1 | 0 | 1 | 0 | 0 | Select 01 → Y1 receives D |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | Select 10 → Y2 receives D |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | Select 11 → Y3 receives D |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | D=0 — all outputs 0 |
Boolean Expression
Outputs 0 and 1: each ANDs D with the matching select decode.
Outputs 2 and 3 — the upper half of the select range.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1D=1S0=0S1=0Expected:
Y0=1, others=0What you'll see:Select 00, D=1 → only Y0 lights up. The other outputs stay dark. - 2D=1S0=0S1=1Expected:
Y2=1, others=0What you'll see:Walk through the select codes — each one routes D to a different output. - 3D=0S0=1S1=1Expected:
All outputs = 0What you'll see:Selected output is Y3, but D=0, so Y3 is 0. The DEMUX is doing its job — non-selected lines are guaranteed 0. - 4D=1S0=1S1=0Expected:
Y1=1, others=0What you'll see:Y1 lights, others stay dark. Try toggling D rapidly while keeping S fixed — only Y1 reflects D.
Components Used
Applications and Design Context
Memory bank write enable. A 2-bit bank selector routes a write-enable pulse to one of 4 memory banks via a 1-to-4 DEMUX.
TDM serial routing. A 4-channel TDM receiver uses a 1-to-4 DEMUX clocked synchronously with the sender to split the time-multiplexed stream back into 4 channels.
State-machine output routing. A FSM in a one-hot encoding routes a common output strobe to the active state's destination via a DEMUX driven by the state select.
Chip-select fan-out. A microcontroller with 4 peripherals can use a 1-to-4 DEMUX to assert exactly one peripheral's chip-select line based on the address-decode result.
Frequently Asked Questions
How is this different from a 2-to-4 decoder?
A decoder has no data input — it just asserts one of N output lines based on select. A DEMUX with D=1 behaves identically. With varying D, the DEMUX additionally passes D's value (not just 1) to the selected output.
Can two outputs be high at once?
No. A DEMUX selects exactly one output to reproduce D; all others are held at 0. Only one minterm of the select bits is 1 at a time. Consequently, when D=1 exactly one output is HIGH, whereas when D=0 all outputs are LOW.
Can this template predict propagation delay?
This packaged behavioral component does not predict physical delay. A gate-level implementation combines select decoding with four data-gating paths; its delay depends on topology, logic family, fan-out, routing, voltage, and load.
How does this scale to 1-to-N for arbitrary N?
1-to-N needs ⌈log₂N⌉ select bits and N output lines. For powers of 2, you can build it as a tree of 1-to-2 DEMUXes — log₂N levels deep, total of N−1 1-to-2 stages.
Where does DEMUX appear in a CPU?
Write-back stage uses DEMUX to route the result to the correct register based on the destination-register field of the instruction. Cache-line fill uses DEMUX to direct the bus data to the correct way of a set-associative cache.