Sequential Instruction Executor (Mini CPU) Simulator

交互式模拟器需要 JavaScript

启用 JavaScript 即可加载实时电路。下方真值表描述了该电路的行为。

您将学到什么

Identify the fetch-decode-execute cycle of a CPU.
Recognize the role of each component: PC, ROM, IR, Control Unit, Register File, ALU, Data Bus.
Trace a single instruction through all four phases.
Connect this to real CPUs — MIPS, RISC-V, ARM, x86.
Appreciate that all of computing reduces to coordinated digital-logic primitives.

工作原理

A sequential instruction executor is a minimal CPU: it fetches instructions from a ROM, decodes them, executes them via an ALU, and updates registers — repeating this fetch-decode-execute cycle on every clock. This is the core architecture of every general-purpose computer.

The key components: - Program Counter (PC): A counter that addresses the next instruction in ROM. Increments each cycle (or jumps for branches). - Instruction ROM: Stores the program. Address = PC; output = current instruction word. - Instruction Register (IR): Latches the fetched instruction for one cycle so the rest of the CPU can decode it. - Control Unit / Decoder: Combinational logic that interprets the IR and asserts control signals (ALU op, register-write enables, MUX selects). - Register File: Holds general-purpose registers (R0..R7 in this demo). - ALU: Performs the operation specified by the decoded instruction. - Data Bus: Routes data between register file, ALU, and memory.

A single instruction execution: 1. Fetch: PC → ROM → IR. 2. Decode: IR → Control Unit → control signals. 3. Execute: Control signals route operands through register file and ALU; result written back to destination register. 4. Increment PC for the next instruction.

This is exactly the structure of any single-cycle RISC CPU (a textbook MIPS or RISC-V model). Production CPUs add pipelining (overlap fetch/decode/execute of consecutive instructions), branch prediction, out-of-order execution, and many other optimizations — but the core fetch-decode-execute loop is the same.

逐步尝试

在上方嵌入式电路中设置输入，然后阅读预期结果并验证。

1

Clock = single edge PC = 0

预期: Fetch first instruction; IR holds it

您将看到: On the first clock edge, the CPU fetches ROM[0] into IR. The control unit's outputs reflect what this instruction commands.
2

Clock = next edge

预期: Decoded operation executes; PC increments

您将看到: Second edge: control signals route operands through the ALU and register file; result is written back. PC ticks to 1, ready for the next instruction.
3

Clock = running

预期: Program runs sequentially through ROM

您将看到: With the clock free-running, the CPU executes instructions one after another. Each clock cycle = one fetch-decode-execute = one instruction completed.
4

Clock = stopped

预期: CPU frozen

您将看到: Stop the clock — the entire CPU freezes mid-instruction. Sequential systems need a clock to evolve.

使用的组件

Clock

×1

Program Counter (8-bit)

实际应用

Microcontrollers. Every microcontroller (Cortex-M, AVR, RISC-V) has this fetch-decode-execute architecture, just with optimisations (pipelining, harvard memory, etc.).

Educational CPUs. University CPU-design courses build this exact circuit — typically a single-cycle MIPS or RISC-V — as the capstone project.

Embedded soft-CPUs in FPGAs. Designers implement small CPUs in FPGA logic (e.g., MicroBlaze, NIOS) using this architecture as a starting point.

Hardware emulators. Old-platform emulators model classic 8-bit CPUs (6502, Z80) using a sequential interpreter that mirrors this architecture in software.

Capstone for digital-logic curriculum. Building a tiny CPU from gates demonstrates that all of computing reduces to the components covered in earlier templates: gates, registers, counters, decoders, MUXes, ALU.

常见问题

What's the difference between this and a real CPU?

Scale and optimization. This single-cycle CPU executes one instruction per clock with no overlap. Real CPUs **pipeline** — overlapping fetch, decode, and execute of consecutive instructions to approach one-instruction-per-clock throughput at much higher clock rates. They also add branch prediction, out-of-order execution, caches, and many other optimizations.

How does the CPU know what each instruction means?

The control unit decodes the IR's bits according to the **instruction set architecture** (ISA). Each opcode maps to a specific pattern of control signals. The ISA is the contract between hardware and software — it defines which bit patterns mean ADD, MOV, JUMP, etc.

How are branches and jumps handled?

A branch instruction tells the control unit to load the PC with a target address instead of incrementing it. Conditional branches additionally test a flag (Z, N, etc.) and branch only if the condition holds. Real CPUs add branch prediction to keep the pipeline full despite jumps.

Where do data values come from for instructions?

Either from registers (specified by the instruction's register fields) or from immediate values embedded in the instruction word itself. Some instructions also read from data memory via address-decoder logic similar to the ROM but writable.

Could I program this CPU?

Yes — define an ISA (set of opcodes), write your program in those opcodes, store them in the ROM at the right addresses. The CPU will execute them. This is the same process used to write programs for any computer, just at a much smaller scale here.