NAND-Only NOT, AND, and OR
Six NAND gates implement NOT A, A AND B, and A OR B as three visible functions. The circuit demonstrates functional completeness through explicit gate-level transformations.
What You'll Learn
- Construct NOT A with one tied-input NAND gate.
- Construct A AND B by inverting a NAND result.
- Construct A OR B from inverted inputs using De Morgan's law.
- Verify the three simultaneously visible outputs for every A/B vector.
- Explain functional completeness without confusing it with implementation optimality.
How It Works
This production circuit uses six NAND gates to construct three familiar functions from the same two switches A and B. Three output lights show NOT A, A AND B, and A OR B. There is no separate light for a raw two-input NAND result.
The NOT branch ties both inputs of one NAND to A, producing ¬(A·A) = ¬A. The AND branch sends A and B into one NAND, then ties both inputs of a second NAND to that intermediate result, canceling the inversion and producing A·B. The OR branch first makes ¬A and ¬B with two tied-input NANDs, then computes ¬(¬A·¬B) = A + B.
These three constructions establish functional completeness: NOT plus either AND or OR is sufficient to synthesize arbitrary Boolean functions. The canvas makes each completed function visible while keeping intermediate nodes internal to their branches.
Truth Table
All three lamps are circuit outputs. For each A/B vector, read them in the order NOT A, A AND B, and A OR B.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| A | B | NOT A | A AND B | A OR B | |
| 0 | 0 | 1 | 0 | 0 | A is low, so NOT A is high; neither AND nor OR is asserted |
| 0 | 1 | 1 | 0 | 1 | Only B is high; OR is asserted while AND remains low |
| 1 | 0 | 0 | 0 | 1 | Only A is high; NOT A is low and OR is asserted |
| 1 | 1 | 0 | 1 | 1 | Both inputs are high; AND and OR are asserted while NOT A is low |
Boolean Expression
Tying both inputs of the first NAND to A makes its visible output ¬A.
A second tied-input NAND inverts NAND(A, B), recovering A·B.
Two tied-input NANDs form ¬A and ¬B; NANDing those values gives A + B by De Morgan's law.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A=0B=0Expected:
NOT A = 1, A AND B = 0, A OR B = 0What you'll see:At 00, the tied-input inverter branch is the only high output. - 2A=0B=1Expected:
NOT A = 1, A AND B = 0, A OR B = 1What you'll see:At 01, the three-NAND OR branch goes high, but the two-NAND AND branch remains low. - 3A=1B=0Expected:
NOT A = 0, A AND B = 0, A OR B = 1What you'll see:At 10, OR remains high and NOT A changes low, showing that the first output depends only on A. - 4A=1B=1Expected:
NOT A = 0, A AND B = 1, A OR B = 1What you'll see:At 11, the reconstructed AND output goes high; all outputs match their named functions.
Components Used
Applications and Design Context
Standard-cell synthesis. NAND cells are common building blocks in ASIC libraries, and synthesis tools use them where they meet timing, area, and power objectives.
Logic normalization. Converting a network into a NAND-oriented form provides a systematic implementation route and supports formal Boolean manipulation.
Discrete logic design. A limited inventory of NAND packages can realize several required functions without stocking a separate gate type for each one.
Safety and control logic. Interlocks and enable equations can be transformed into NAND structures when that matches the target hardware.
Digital-logic education. The three visible branches make De Morgan transformations observable at the signal level.
Frequently Asked Questions
Why is NAND called a universal gate?
A gate set is functionally complete when every Boolean function can be composed from it. Because NAND can realize NOT and then use that inversion to realize AND and OR, arbitrary combinational logic can be expressed with NAND alone.
How does a tied-input NAND become NOT?
When both inputs receive A, the NAND computes ¬(A·A). Since A·A = A, the result is ¬A. One NAND is therefore sufficient for the visible NOT A branch.
Why does the AND branch require two NAND gates?
The first NAND produces ¬(A·B). The second has both inputs tied to that intermediate signal and inverts it, yielding A·B. The intermediate NAND value is not presented as a separate circuit output.
How does the OR branch work?
The circuit first generates ¬A and ¬B with two tied-input NANDs. A third NAND produces ¬(¬A·¬B), which equals A + B. This is a direct application of De Morgan's law.
Should every circuit be implemented with NAND gates only?
Not necessarily. Logic synthesis considers delay, area, power, loading, and the available technology library. Universality guarantees that a NAND-only realization exists; it does not guarantee that it is the best physical implementation.