Reference

Digital Logic Glossary

Concise definitions of the core terms in digital logic and circuit design — from gates and Boolean algebra to flip-flops, ALUs, and CPU architecture. Each entry is one citable sentence followed by a short clarifier and links to a deeper tutorial.

63 terms · 8 categories

Fundamentals

# Binary (Base-2): Binary is the base-2 number system: every value is encoded as a sequence of 0s and 1s. Digital electronics represent these as two voltage levels (LOW and HIGH), making binary the natural language of computers. Deep dive →
# Bit: A bit is the smallest unit of digital information — a single 0 or 1. Eight bits make a byte. Every digital signal, value, and instruction is ultimately a sequence of bits.
# Digital Signal: A digital signal is an electrical signal restricted to two valid voltage ranges, typically interpreted as 0 (LOW) and 1 (HIGH). Anything between those ranges is invalid logic and signals a fault or a metastable state. Component docs →
# Truth Table: A truth table is a complete enumeration of every possible input combination of a digital function and the output it produces. For an n-input gate it has 2ⁿ rows. Truth tables define what a circuit *does*, independent of how it is built. Deep dive →
# Active-High / Active-Low: An active-high signal triggers its function when driven to logic 1; an active-low signal triggers when driven to 0. Reset pins, chip-select lines, and many control signals are active-low because driving a pin to ground is more reliable than relying on the absence of noise.

Logic Gates

# Logic Gate: A logic gate is a digital component that computes a Boolean function of its inputs. The seven most common gates are AND, OR, NOT, NAND, NOR, XOR, and XNOR. Every digital circuit, from a single-bit comparator to a CPU, is built from logic gates. Deep dive →
# AND Gate: An AND gate outputs 1 only when all of its inputs are 1; otherwise it outputs 0. Boolean expression: Y = A · B. The AND gate models the "all conditions must be met" pattern that appears in safety interlocks, multi-key locks, and address decoders. Deep dive →Component docs →
# OR Gate: An OR gate outputs 1 if at least one input is 1, and 0 only when every input is 0. Boolean expression: Y = A + B. The OR gate models the "any condition is sufficient" pattern used in alarm circuits and multi-source triggers. Deep dive →Component docs →
# NOT Gate (Inverter): A NOT gate (inverter) takes a single input and produces its logical complement: 0 becomes 1, and 1 becomes 0. Boolean expression: Y = A̅. NOT gates are essential for active-low signals, output negation, and converting between dual gate families. Deep dive →Component docs →
# NAND Gate: A NAND gate is an AND gate followed by a NOT — it outputs 0 only when all inputs are 1. Boolean expression: Y = (A · B)̅. NAND is functionally complete: every other Boolean function can be built from NAND gates alone, which is why it dominates CMOS silicon. Deep dive →Component docs →
# NOR Gate: A NOR gate is an OR followed by a NOT — it outputs 1 only when every input is 0. Boolean expression: Y = (A + B)̅. Like NAND, NOR is functionally complete; the Apollo Guidance Computer was famously built from NOR gates alone. Deep dive →Component docs →
# XOR Gate (Exclusive OR): An XOR (exclusive-OR) gate outputs 1 when its inputs differ and 0 when they match. Boolean expression: Y = A ⊕ B. XOR is the heart of every binary adder (it computes the sum bit), parity checker, and many error-detection schemes. Deep dive →Component docs →
# XNOR Gate (Equivalence Gate): An XNOR gate is the complement of XOR — it outputs 1 when its inputs are equal. Boolean expression: Y = (A ⊕ B)̅. XNOR is the comparator primitive: a stack of XNORs followed by an AND tells you whether two binary words are identical. Deep dive →Component docs →
# Buffer: A buffer is a single-input single-output gate that simply copies its input to its output. Buffers exist not for logic but for electrical reasons: they restore signal strength on long traces, drive heavy loads (high fan-out), and provide tri-state isolation. Deep dive →Component docs →
# Tri-State Buffer: A tri-state buffer has three possible output states: 0, 1, and high-impedance (Z). When disabled, the output disconnects from the bus, allowing many devices to share a single wire. Tri-state buffers are how every shared bus in a CPU works. Component docs →
# Universal Gate: A universal gate is one from which any other Boolean function can be built. NAND and NOR are the only two-input gates with this property. CMOS chip designs exploit this by building entire logic families from NAND-only or NOR-only cells. Deep dive →
# Functional Completeness: A set of gates is functionally complete if every possible Boolean function can be expressed using only those gates. {AND, OR, NOT}, {NAND}, and {NOR} are each functionally complete. Functional completeness is the formal property that justifies calling NAND/NOR "universal".

Boolean Algebra

# Boolean Algebra: Boolean algebra is the mathematics of two-valued logic, defined by George Boole in 1854. It uses three primitive operations — AND (·), OR (+), and NOT (̅) — and a small set of laws (identity, null, complement, absorption, De Morgan, distributive) to manipulate logical expressions. Deep dive →
# De Morgan's Laws: De Morgan's Laws state that (A · B)̅ = A̅ + B̅ and (A + B)̅ = A̅ · B̅. They allow any AND-OR circuit to be rewritten as a NAND-only or NOR-only circuit, which is why they sit at the heart of CMOS gate-level optimization. Deep dive →
# Sum of Products (SOP) (SOP, Minterm Form): Sum of Products is a canonical Boolean form: an OR of AND-terms (minterms), one minterm per row of the truth table where the output is 1. SOP maps directly to a two-level AND-OR or NAND-NAND circuit. Deep dive →
# Product of Sums (POS) (POS, Maxterm Form): Product of Sums is the dual canonical form of SOP: an AND of OR-terms (maxterms), one per row of the truth table where the output is 0. POS maps directly to a two-level OR-AND or NOR-NOR circuit. Deep dive →
# Karnaugh Map (K-map): A Karnaugh map is a graphical method for simplifying Boolean expressions of up to ~6 variables. Adjacent 1-cells are grouped into rectangles whose sizes are powers of two, and each group corresponds to a simplified product term. Deep dive →
# Minterm: A minterm is a product term that is 1 for exactly one row of a truth table. For n inputs there are 2ⁿ possible minterms. ORing the minterms of all output-1 rows gives the canonical SOP expression.
# Maxterm: A maxterm is a sum term that is 0 for exactly one row of a truth table. ANDing the maxterms of all output-0 rows gives the canonical POS expression — the dual of the minterm/SOP construction.

Combinational Logic

# Combinational Logic: Combinational logic is any digital circuit whose outputs depend only on its current inputs, with no memory of previous states. Adders, decoders, multiplexers, and ALUs are combinational. Contrast with sequential logic, which has internal state.
# Multiplexer (MUX) (MUX, Data Selector): A multiplexer routes one of 2ⁿ data inputs to a single output, controlled by n select lines. Multiplexers are universal function generators: any Boolean function of n inputs can be implemented with a single 2ⁿ-to-1 MUX. Deep dive →Component docs →
# Demultiplexer (DEMUX) (DEMUX): A demultiplexer is the inverse of a MUX: it routes a single input to one of 2ⁿ outputs based on n select lines. DEMUX circuits are how a CPU dispatches data to one of many destination registers or memory banks. Component docs →
# Decoder: A decoder converts an n-bit binary input into a one-hot output of 2ⁿ lines, asserting exactly one output at a time. Address decoders inside RAM, BCD-to-7-segment converters, and instruction decoders are all decoder circuits. Deep dive →Component docs →
# Encoder: An encoder is the inverse of a decoder: it converts a one-hot 2ⁿ-line input into an n-bit binary output. Priority encoders extend this by handling multiple simultaneous active inputs and outputting the highest-priority one. Deep dive →Component docs →

Sequential Logic

# Sequential Logic: Sequential logic is any digital circuit whose outputs depend on both its current inputs and its stored internal state. Latches, flip-flops, registers, counters, and CPUs are all sequential. State is updated on clock edges (synchronous) or on input changes (asynchronous).
# Latch: A latch is a level-sensitive 1-bit memory element: its output follows its input as long as a control signal (Enable) is asserted. When Enable goes inactive, the latch holds its last value. The SR latch and D latch are the two canonical examples.
# SR Latch (Set-Reset Latch): An SR latch has two inputs (Set and Reset) and one output. Asserting Set drives the output to 1; asserting Reset drives it to 0; asserting neither holds the previous state. Asserting both is forbidden — the output becomes undefined. Deep dive →Component docs →
# D Latch: A D latch has a single Data input and an Enable line. When Enable is HIGH the output transparently follows D; when Enable goes LOW, the latch holds whatever value was on D at that moment. The D latch fixes the SR latch's forbidden state. Deep dive →Component docs →
# Flip-Flop: A flip-flop is an edge-triggered 1-bit memory element: it samples its input only on a single clock transition (typically the rising edge) and ignores it the rest of the time. This zero-width capture window is what makes synchronous digital design possible.
# D Flip-Flop: A D flip-flop captures its data input D on each active clock edge and holds that value until the next active edge. Q(t+1) = D. The D flip-flop is the basic storage cell behind every register, counter, and CPU pipeline stage. Deep dive →Component docs →
# JK Flip-Flop: A JK flip-flop generalizes the SR flip-flop by redefining J=K=1 as a toggle (instead of forbidden). It can hold, set, reset, or toggle, making it the universal building block of synchronous counters and many state machines. Deep dive →Component docs →
# T Flip-Flop: A T (toggle) flip-flop has a single input T: when T=1, the output toggles on each clock edge; when T=0, it holds. T flip-flops are frequency dividers — chain n of them and the last output toggles at f/2ⁿ. Deep dive →Component docs →
# Register: A register is a group of flip-flops sharing a common clock, used to store an n-bit word. A 4-bit register stores a nibble; an 8-bit register stores a byte. Registers are the basic addressable storage cells inside a CPU. Deep dive →Component docs →
# Shift Register: A shift register is a chain of flip-flops in which each Q output feeds the next D input, so on each clock edge the stored bits shift one position. Shift registers convert serial data to parallel (SIPO) and back (PISO). Deep dive →Component docs →
# Counter: A counter is a sequential circuit that cycles through a fixed sequence of binary states, advancing on each clock edge. Binary counters count 0,1,2,…,2ⁿ-1; modulo-N counters reset after N states; Johnson and ring counters use shift-register topologies. Deep dive →Component docs →
# Finite State Machine (FSM) (FSM, State Machine): A finite state machine is a sequential circuit whose next state depends on its current state and inputs, defined by a fixed transition table. FSMs implement protocols, traffic-light controllers, and the control logic of every CPU. Deep dive →

Arithmetic Circuits

# Half Adder: A half adder adds two single bits and produces a 2-bit result: a sum (XOR of the inputs) and a carry (AND of the inputs). It cannot accept a carry-in, so it can only be the lowest bit of a multi-bit adder. Deep dive →Component docs →
# Full Adder: A full adder adds three single bits — two operands plus a carry-in — and produces a 2-bit result: sum and carry-out. Cascading n full adders builds an n-bit ripple-carry adder. Deep dive →Component docs →
# Ripple-Carry Adder: A ripple-carry adder chains n full adders so each carry-out feeds the next carry-in. It's the simplest n-bit adder topology, but its propagation delay is proportional to n — which is why high-speed CPUs use carry-lookahead variants instead. Deep dive →
# Arithmetic Logic Unit (ALU) (ALU): An ALU is the combinational unit inside a CPU that performs integer arithmetic (ADD, SUB) and bitwise logic (AND, OR, XOR, NOT). It typically outputs both the result and condition flags (zero, carry, negative, overflow) consumed by branch instructions. Component docs →

CPU & Memory

# Program Counter (PC) (PC): The Program Counter is the register that holds the memory address of the next instruction to fetch. It increments after each fetch and is overwritten by branch and jump instructions to redirect execution. Deep dive →Component docs →
# Instruction Register (IR) (IR): The Instruction Register is the register that holds the instruction currently being decoded and executed. The Control Unit reads its bit fields (opcode, register addresses, immediate values) to derive control signals. Component docs →
# Control Unit: The Control Unit decodes the instruction in the IR and generates the control signals that orchestrate every other CPU component: which registers to read, which ALU operation to perform, when to write back results, and when to fetch the next instruction. Component docs →
# Fetch-Decode-Execute Cycle (Instruction Cycle): The fetch-decode-execute cycle is the three-phase loop every von Neumann CPU repeats: fetch the next instruction from memory, decode it to determine the operation, then execute that operation. Modern pipelined CPUs overlap these phases across many instructions. Deep dive →
# RAM (Random-Access Memory): RAM is volatile read-write memory in which any address can be accessed in roughly the same time. It loses its contents when power is removed. CPU caches, main memory, and register files are all forms of RAM. Component docs →
# ROM (Read-Only Memory): ROM is non-volatile memory that retains its contents without power. It is typically programmed at manufacturing time (mask ROM) or with a one-time write (PROM/EPROM). Boot code, microcode, and lookup tables are commonly stored in ROM. Component docs →
# Bus: A bus is a shared set of wires that carries data, addresses, or control signals between multiple components. Tri-state buffers let many devices share the bus while only one drives it at a time. Component docs →

Timing & Physics

# Clock Signal: A clock is a periodic square wave that synchronizes every flip-flop in a digital system. Its rising and falling edges are when state changes happen; its frequency sets how many operations the system performs per second. Deep dive →Component docs →
# Edge-Triggered: An edge-triggered element changes state only at a specific clock transition — usually the rising edge. This contrasts with level-sensitive (transparent) latches, which follow their input as long as Enable is asserted. Edge-triggering is what makes synchronous design predictable.
# Setup Time (t_su): Setup time is the minimum interval the data input of a flip-flop must be stable *before* the active clock edge. Violating setup time can drive the flip-flop into a metastable state where its output is neither 0 nor 1. Deep dive →
# Hold Time (t_hold): Hold time is the minimum interval the data input must remain stable *after* the active clock edge. Violating hold time, like violating setup, can cause metastability or incorrect capture. Deep dive →
# Propagation Delay (t_pd, Gate Delay): Propagation delay is the time between an input change and the resulting output change of a gate. Cumulative propagation delay along the longest path in a circuit (the *critical path*) sets the system's maximum clock frequency. Deep dive →
# Metastability: Metastability is an unstable equilibrium state a flip-flop can enter when its setup or hold time is violated — neither 0 nor 1, but a slowly resolving intermediate voltage. The standard fix is a two-stage synchronizer: two flip-flops in series clocked by the destination domain's clock. Deep dive →
# Synchronizer: A synchronizer is a chain of flip-flops (typically two) used to safely move a signal from one clock domain into another. The first stage may go metastable; by the second clock edge, it has almost certainly resolved, making the second stage safe to use downstream. Deep dive →
# Clock Domain Crossing (CDC) (CDC): Clock-domain crossing is the act of transferring a signal between two parts of a circuit that run on unrelated clocks. Naive transfers cause metastability; correct CDC uses synchronizers, async FIFOs, or handshakes plus Gray-code encoding for multi-bit values.
# Fan-Out: Fan-out is the number of gate inputs a single output drives. Each load adds capacitance and slows the signal; exceeding a gate's specified fan-out causes weak logic levels and timing failures. Buffers are inserted to relieve high-fan-out nodes.
# CMOS (Complementary MOS): CMOS is the dominant integrated-circuit technology, pairing NMOS and PMOS transistors in complementary structures so that essentially no current flows in steady state. Every modern CPU, GPU, and microcontroller is built in CMOS.
# Frequency Division: Frequency division produces a slower clock from a faster one by toggling a flip-flop every n input cycles. A T flip-flop divides by 2; an N-bit binary counter divides by 2ⁿ; modulo-N counters divide by arbitrary integers. Deep dive →

Build the circuits behind these definitions

Every term above corresponds to a component or circuit you can wire together in your browser. Open the simulator and start with a NAND gate.

Start with Digital Logic 101 Browse component docs