8-Bit Counter with Controls Circuit Simulator

Interactive simulator requires JavaScript

Enable JavaScript to load the live circuit. The truth table below describes the circuit's behaviour.

Open in Full Simulator Browse All Templates

What You'll Learn

Use enable, reset, and parallel-load to control an 8-bit counter.
Count from 0 to 255 then wrap.
Recognize the priority: Reset > Load > Enable > Hold.
Apply parallel-load + count for programmable frequency dividers.
Connect this to microcontroller hardware timers and DMA address generators.

How It Works

An 8-bit counter with controls is a binary counter that can count from 0 to 255, with enable (gates clock-driven counting), reset (sync or async clear to 0), and parallel load (preset to any value).

The counter is synchronous — all 8 flip-flops share the same clock. Each clock edge: - If RESET is asserted: count = 0 (regardless of other inputs). - Else if LOAD is asserted: count = D[7:0] (parallel load from inputs). - Else if ENABLE is asserted: count = current_count + 1. - Else: count holds.

With 8 bits the counter wraps from 255 (0xFF) back to 0 after the 256th clock edge. The carry-out signal pulses high when the counter is at 255 and ENABLE is high, allowing chaining to a higher-order counter for >256 ranges.

This cell is directly equivalent to a 74xx169 / 161 / 163 TTL counter chip, used in countless real designs for timing, address generation, and frequency division.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

EN = 1 RST = 0 LOAD = 0 Clock = running

Expected: Counter cycles 0..255 then wraps

What you'll see: Standard count-up. Watch the lights and digit display increment each clock.
2

EN = 0 RST = 0 LOAD = 0 Clock = running

Expected: Counter holds

What you'll see: Enable low — clock edges arrive but counter doesn't increment. Used for pause/stall.
3

RST = 1 Clock = running

Expected: Counter forced to 0

What you'll see: Asserting reset clears the counter immediately. Useful for restart or initialization.
4

LOAD = 1 D = 100 Clock = rising

Expected: Counter = 100

What you'll see: Parallel load sets counter to a specific value. From there, normal count-up takes it to 101, 102, ... up to 255 before wrapping.

Components Used

Real-World Applications

Microcontroller hardware timers. ARM Cortex-M and AVR microcontrollers have 8/16/32-bit counters with these exact controls — used for PWM generation, periodic interrupts, and pulse measurement.

Memory address generation. A counter increments through addresses in DMA transfers, with LOAD setting the start address and ENABLE gated by the DMA-active signal.

Audio sample-rate generators. Counters in audio codec ICs divide a master clock down to the sample rate (44.1 kHz, 48 kHz) using LOAD-based programmability.

Frequency dividers (programmable). A counter that LOADs a divisor and counts up to it before resetting produces an arbitrary divide-by-N clock — much more flexible than fixed power-of-2 dividers.

Pulse counting in instruments. Lab counters and frequency meters use wide counters with these controls to capture event counts in a measurement window.

Frequently Asked Questions

What's the priority of the control signals?

Typically Reset > Load > Enable > Hold. Reset always wins; if not asserted, Load takes precedence over Enable; if neither, Enable allows counting; otherwise hold.

Can this be a down-counter?

Some implementations include a direction control (UP/DN) that switches between increment and decrement. This circuit is up-only; a UP/DOWN version uses 2-to-1 MUXes on the next-state logic to pick between count+1 and count-1.

How would I make this count modulo-100?

Decode count = 99 with an AND gate; on the next clock edge, the LOAD input asserts and loads 0 (or 100 - N for any modulus). Or use the synchronous reset when count = 99. Either way: count cycles 0..99 then back to 0.

What's the carry-out for cascading?

TC (terminal count) or RCO (ripple carry out) goes high when the counter reaches its max (255 for 8-bit). It can drive the ENABLE of a higher-order counter, so the higher counter increments only once per 256 ticks of the lower one.

How fast can this run?

Limited by the longest path between flip-flops — typically the carry chain from bit 0 to bit 7. With carry-lookahead acceleration, modern CMOS counters run at multi-GHz. Without lookahead, the ripple-carry path is slower for wide counters.