8-Bit Counter with Enable and Clear
The counter advances modulo 256 on rising edges when EN is HIGH and clears asynchronously when CLR is HIGH. Its connected LD switch is reserved by the current evaluator and does not load a value; two hexadecimal displays show 00 through FF.
What You'll Learn
- Use enable and asynchronous clear to control an 8-bit counter.
- Count from 0 to 255 then wrap.
- Apply the actual priority: CLR > enabled rising-edge increment > hold.
- Verify that the wired LD input is reserved and has no implemented effect.
- Read the byte from two hexadecimal displays and eight Q traces.
How It Works
The COUNTER_8BIT has four control pins: CLK, CLR, EN, and LD. CLR is active high and asynchronous; CLR = 1 immediately sets the stored count to 0. With CLR = 0, a rising clock edge increments the count modulo 256 only when EN = 1. EN = 0 holds the current value.
The LD pin is connected to a switch but is explicitly reserved in the current evaluator. The component has no parallel data input pins and LD does not load a value or otherwise change the count. Describing this circuit as parallel-load capable would therefore be incorrect.
Q0..Q7 feed the eight oscilloscope channels. Q0..Q3 also feed the lower hexadecimal display, while Q4..Q7 feed the upper display, yielding a visible range 00–FF. The terminal-count output exists on the component but is unconnected.
Boolean Expression
Active-high CLR asynchronously forces the stored eight-bit count to zero.
With CLR low and EN high, each rising edge increments the count modulo 256.
With no asserted clear and either no rising edge or EN low, the count holds; LD does not alter this evaluator.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1CLR=0Clock=runningEN=1LD=0Expected:
The count increments modulo 256 on each rising edgeWhat you'll see:Set CLR = 0 and EN = 1. Each rising edge increments the two-digit hexadecimal value; FF wraps to 00. - 2CLR=0Clock=runningEN=0LD=0Expected:
The current count is retainedWhat you'll see:Set EN = 0 while CLR remains 0. Additional rising edges do not change either display or any Q trace. - 3CLR=1Clock=any levelExpected:
The count becomes 0 immediatelyWhat you'll see:Set CLR = 1. The count clears immediately, without waiting for CLK. - 4CLR=0Clock=risingEN=0LD=0 → 1Expected:
The count remains unchanged because LD is reserved and has no implemented load data pathWhat you'll see:Release CLR, keep EN = 0, and toggle LD from 0 to 1 across a rising edge. The count holds because LD has no implemented data path.
Components Used
Applications and Design Context
Event counting. An enable can restrict counting to a defined observation interval.
Address sequencing. A modulo-256 up-counter can generate a repeating byte-wide address sequence when no programmable start address is required.
Frequency division. Individual Q bits of a binary count change at successively lower rates.
Digital instrumentation. Hexadecimal displays and per-bit waveforms provide two complementary views of the same stored count.
Frequently Asked Questions
What is the actual control priority?
CLR has asynchronous priority. With CLR = 0, EN = 1 increments on a rising edge and EN = 0 holds. Although an LD pin is present and wired to a switch, the current counter evaluator reserves it for future use and performs no parallel load.
Can this be a down-counter?
No. The implemented primitive increments only. It has no connected direction input or decrement behavior.
How do the two digit displays represent the byte?
Q0..Q3 drive the lower hexadecimal digit and Q4..Q7 drive the upper digit. Together they display the counter as 00 through FF.
Is terminal count used?
The primitive has a terminal-count output that is high at 255, but that pin is unconnected in this production circuit. There is no visible carry indicator or cascaded counter.
Which signals are plotted?
The 8-channel oscilloscope receives Q0 through Q7. The clock and control inputs are not connected to scope channels, and there are no output-light components.