4-Bit Magnitude Comparator
Eight switches define unsigned operands A and B, and three mutually exclusive lights report A greater than B, A equal to B, or A less than B. This canonical content identity also serves Production runtime template 126 through an explicit reviewed alias.
This circuit compares two unsigned 4-bit words, A and B, over the range 0–15. Exactly one result indicates whether A is greater than, equal to, or less than B.
What You'll Learn
- Interpret A > B, A = B, and A < B as mutually exclusive comparison results.
- Relate the A3..A0 and B3..B0 switch patterns to unsigned values from 0 through 15.
- Explain why the most-significant unequal bit determines magnitude.
- Derive equality and ordered-comparison equations from bitwise XNOR terms.
- Apply magnitude comparison to branch, threshold, and selection logic.
How It Works
The input switches define A3..A0 and B3..B0, with bit 3 as the most-significant bit and bit 0 as the least-significant bit. The comparator evaluates the most-significant unequal bit: if A3 and B3 differ, that pair determines the result; otherwise the decision proceeds toward bit 0. If all four pairs match, the equality output is asserted.
The three outputs form a one-hot relation for fully defined binary inputs. A > B, A = B, and A < B are mutually exclusive, and one of them is always HIGH. Equality can be formed by XNOR-comparing corresponding bits and ANDing the four matches. The greater-than and less-than networks qualify each lower-bit decision with equality of every more-significant pair.
This priority from the most-significant bit is what distinguishes a magnitude comparator from four independent equality checks. For example, A = 1000₂ is greater than B = 0111₂ even though three lower bit positions favor B, because the bit-3 decision has the greatest weight.
Truth Table
A complete 4-bit comparator has 256 input combinations. These representative vectors cover equality, both ordered outcomes, and decisions at different bit positions; outputs are ordered A > B, A = B, A < B.
| Inputs | Output | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| A3 | A2 | A1 | A0 | B3 | B2 | B1 | B0 | A > B | A = B | A < B | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Both operands are zero, so equality is asserted. |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | The least-significant bit makes A greater than B. |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | The least-significant bit makes A less than B. |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | All corresponding bits match for decimal 7. |
| 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Bit 3 decides the result: 8 is greater than 7. |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Bit 3 decides the result: 7 is less than 8. |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | The operands agree through bit 1; bit 0 makes 15 greater than 14. |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | The operands agree at bit 3; bit 1 makes 9 less than 11. |
Boolean Expression
Xi is HIGH when the corresponding bits Ai and Bi are equal.
All four bit-pair equality terms must be HIGH for A = B.
A is greater when the first unequal pair, scanning from bit 3 to bit 0, has Ai = 1 and Bi = 0.
A is less when the first unequal pair has Ai = 0 and Bi = 1.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A3..A0=0000B3..B0=0000Expected:
A = B is HIGH; A > B and A < B are LOWWhat you'll see:With both words at 0000₂, only the equality light is active. - 2A3..A0=1001B3..B0=0110Expected:
A > B is HIGHWhat you'll see:1001₂ is decimal 9 and 0110₂ is decimal 6, so the greater-than result is active. - 3A3..A0=0011B3..B0=1100Expected:
A < B is HIGHWhat you'll see:0011₂ is decimal 3 and 1100₂ is decimal 12, so the less-than result is active. - 4A3..A0=1111B3..B0=1110Expected:
A > B is HIGH; only the least-significant bit differsWhat you'll see:1111₂ and 1110₂ match in their three most-significant positions. The final bit establishes 15 > 14.
Components Used
Applications and Design Context
Processor condition logic. Comparators support unsigned branch conditions, minimum/maximum selection, and limit checks.
Set-point control. A digital controller compares a measured code with a reference before enabling heating, cooling, charging, or an alarm.
Priority and arbitration logic. Systems compare counters, timestamps, or identifiers to select an older, newer, larger, or smaller request.
Sorting and range classification. Comparator stages order fixed-width values or determine whether a value lies inside an allowed interval.
Address and threshold monitoring. Digital instruments use magnitude comparisons to detect terminal counts and configurable trigger levels.
Frequently Asked Questions
Does this comparator treat the inputs as signed or unsigned?
Unsigned. A3..A0 and B3..B0 represent values from 0 through 15. Signed two's-complement comparison requires special treatment of the sign bit or an arithmetic subtraction-and-flags implementation.
Why can only one comparison output be HIGH?
For two fully defined numbers, exactly one mathematical relation is true: A is greater than B, equal to B, or less than B. The comparator implements those three disjoint and exhaustive cases.
Why are the most-significant bits checked first?
A higher bit has greater binary weight than the sum of all lower bits. Once a more-significant pair differs, no lower-bit pattern can reverse that decision.
How is a wider comparator built?
The same bitwise equality and priority relation is extended across more positions, often hierarchically. Integrated comparators may expose cascade inputs and outputs so several devices can compare wider words.
Can subtraction implement the same comparison?
Yes. An ALU can subtract B from A and interpret zero, carry or borrow, sign, and overflow flags according to the required signed or unsigned relation. A dedicated comparator produces the relation directly without retaining a difference word.