Packaged Half-Adder Demonstration
One HALF_ADDER component computes Sum and Carry from two one-bit operands. Separate digit displays show A, B, and the combined two-bit result.
What You'll Learn
- Use a packaged HALF_ADDER through its two-input, two-output interface.
- Interpret the three digit displays for A, B, and the combined result.
- Relate Sum and Carry to XOR and AND without treating hidden gates as canvas components.
- Verify all four input combinations against the half-adder truth table.
- Explain how component abstraction supports hierarchical circuit design.
How It Works
This circuit demonstrates a packaged HALF_ADDER component. Two input switches drive its A and B pins. The component exposes Sum and Carry outputs, which connect to bits 0 and 1 of one result digit display. Two additional digit displays mirror A and B.
The logical behavior is: - Sum = A ⊕ B - Carry = A · B
The result display interprets Carry,Sum as a two-bit unsigned number. It therefore reads 0 for 00, 1 for 01, and 2 for 10. The display does not perform the addition; it only presents the two output bits generated by the half adder.
This production circuit contains one HALF_ADDER, two input switches, and three digit displays. It does not contain visible XOR or AND components. The gate-level implementation is intentionally hidden behind the HALF_ADDER interface, illustrating the move from individual gates to reusable functional blocks.
Truth Table
Sum and Carry are the HALF_ADDER output pins; the result digit display receives Sum as bit 0 and Carry as bit 1.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| A | B | Sum | Carry | Result display | |
| 0 | 0 | 0 | 0 | 0 | 0 + 0 = 00; result display reads 0 |
| 0 | 1 | 1 | 0 | 1 | 0 + 1 = 01; result display reads 1 |
| 1 | 0 | 1 | 0 | 1 | 1 + 0 = 01; result display reads 1 |
| 1 | 1 | 0 | 1 | 2 | 1 + 1 = 10; result display reads 2 |
Boolean Expression
The packaged component exposes the same Sum and Carry function as an XOR-plus-AND gate-level half adder.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A=0B=0Expected:
Sum = 0, Carry = 0, result display = 0What you'll see:Both input displays read 0; Sum and Carry are both low, so the result display reads 0. - 2A=1B=0Expected:
Sum = 1, Carry = 0, result display = 1What you'll see:With one input high, Sum is 1 and Carry is 0; the result display reads 1. - 3A=1B=1Expected:
Sum = 0, Carry = 1, result display = 2What you'll see:With both inputs high, Sum is 0 and Carry is 1; the result display reads binary 10, or decimal 2.
Components Used
Applications and Design Context
Hierarchical arithmetic design. Larger adders are assembled from verified bit-level blocks rather than redrawing every internal gate.
ASIC standard-cell mapping. Synthesis tools can select arithmetic cells characterized for a target process while preserving the same logical interface.
FPGA carry resources. FPGA tools map addition to device-specific lookup-table and carry-chain resources instead of a literal drawing of discrete gates.
Educational comparison. Viewing both packaged and gate-level half adders separates interface behavior from implementation detail.
Reusable verification. Once the component contract is tested for all four input cases, higher-level circuits can instantiate it as a trusted unit.
Frequently Asked Questions
Is the packaged component faster than separate gates?
The two versions are logically equivalent, but this simulation does not establish a physical speed comparison. Delay and area depend on how a target technology implements the packaged function; here, the component mainly provides a cleaner abstraction boundary.
What do the three digit displays show?
The A and B displays mirror the two input switches. The result display receives Sum on bit 0 and Carry on bit 1, so it converts the two-bit result 00, 01, or 10 into the decimal value 0, 1, or 2.
Can the component's internal gates be inspected here?
The production canvas presents HALF_ADDER as an opaque component with two inputs and two outputs. The separate 1-Bit Half Adder template exposes an equivalent XOR and AND implementation for gate-level study.
How does this function extend to a full adder?
A full adder adds a third input, Cin, and produces Sum and Cout. It can be decomposed into two half adders plus an OR gate, or represented by a packaged FULL_ADDER component.
Why are packaged arithmetic components useful?
Hierarchical hardware design relies on verified modules with stable interfaces. Synthesis may map an arithmetic operator to dedicated carry hardware, standard cells, or a gate network, but the designer can reason about the same Sum/Carry contract at the component level.