JK Flip-Flop Master-Slave Circuit Simulator

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What You'll Learn

Recognize the four JK input modes: hold, reset, set, toggle.
Use J=K=1 as a toggle command — the key advantage over SR.
Understand master-slave construction and how it solves the race-around problem.
Build a divide-by-2 frequency divider using JK in toggle mode.
Distinguish JK from D flip-flops and pick the right one per use case.

How It Works

A JK flip-flop generalizes the SR flip-flop by reinterpreting the forbidden state (S=R=1) as a toggle command (J=K=1 means flip Q to its complement). It's edge-triggered, typically built from a master-slave pair of latches.

Behaviour at the rising clock edge: - J=0, K=0: Hold (Q stays the same). - J=0, K=1: Reset (Q = 0). - J=1, K=0: Set (Q = 1). - J=1, K=1: Toggle (Q = ¬Q — flips on every clock edge).

The toggle behaviour makes JK flip-flops useful for counters: tying both J and K to 1 makes the FF flip on every clock, dividing the clock frequency by 2. Cascading several JK flip-flops in toggle mode produces a binary counter — exactly the pattern used in ripple counters.

Master-slave construction: two cross-coupled latches in series with opposite clock phases. The master responds while clock is low; the slave passes the master's value through while clock is high. The crucial race-around problem of the JK in toggle mode (where Q would oscillate during clock-high if it could) is solved by master-slave timing: only the rising edge propagates a single Q transition.

JK flip-flops are less common in modern designs (D flip-flops with an XOR gate on D give equivalent behaviour with fewer transistors), but they're a standard textbook topic and appear in some standard cell libraries.

Truth Table

JK behaviour at the rising clock edge. Toggle (J=K=1) is the unique JK feature.

Inputs		Output
J	K	Q (next)
0	0	0	Hold — Q unchanged
0	1	0	Reset — Q = 0
1	0	1	Set — Q = 1
1	1	1	Toggle — Q flips (here from 0 to 1)

Boolean Expression

Q_{n+1} = J\overline{Q}_n + \overline{K}Q_n

Characteristic equation: J sets a 0 to 1; K resets a 1 to 0. The four combinations cover all behaviours.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

J = 0 K = 0 CLK = rising

Expected: Q unchanged

What you'll see: Hold mode — clock edge does nothing. Q stays at its current value.
2

J = 1 K = 0 CLK = rising

Expected: Q = 1

What you'll see: Set mode — Q goes to 1 on the edge. Clock edge required (no async behaviour).
3

J = 0 K = 1 CLK = rising

Expected: Q = 0

What you'll see: Reset mode — Q goes to 0. Same edge-triggered timing as Set.
4

J = 1 K = 1 CLK = running

Expected: Q toggles every clock edge

What you'll see: Toggle mode — Q flips back and forth on each rising edge. Watch the output light blink at half the clock frequency. This is the divide-by-2 behavior used in ripple counters.

Components Used

Real-World Applications

Binary counter cells. A JK flip-flop with J=K=1 toggles on every clock edge — exactly a divide-by-2 stage. Cascading N of them produces an N-bit ripple counter.

T flip-flop construction. A T flip-flop is a JK with J and K tied together. JK is more general; T is the specialization for toggle-only behaviour.

Mode-controlled state machines. When the FSM needs distinct set/reset/toggle/hold transitions per state, JK's 4 modes match neatly without external multiplexing.

Educational stepping stone. JK flip-flops bridge SR latches (forbidden state) and D flip-flops (single data input) by repurposing the forbidden state into the useful toggle behaviour.

Asynchronous frequency dividers. Older clock-divider circuits used JK in toggle mode for simple divide-by-2N chains — straightforward, low transistor count.

Frequently Asked Questions

Why is JK better than SR?

It eliminates the forbidden state. Where SR's J=K=1 is undefined and dangerous, JK's J=K=1 is well-defined as toggle — useful for counters and frequency dividers. JK turns a bug into a feature.

What's the master-slave advantage?

Solves the race-around problem in toggle mode. Without master-slave, J=K=1 with clock high would cause Q to oscillate continuously during the high phase. Master-slave restricts changes to a single edge per clock cycle.

Why are JK flip-flops less common today?

D flip-flops + XOR achieve the same functionality with simpler logic and better cell-library coverage. Modern synthesis tools generally prefer DFFs. JK is still useful as a teaching tool and in legacy designs.

How do I make a T flip-flop from a JK?

Tie J and K together and label the combined input T. T=0 gives hold, T=1 gives toggle. T flip-flops are simpler than JK and useful for frequency dividers.

Can JK be edge-triggered without master-slave?

Pure-edge JK flip-flops exist (sense-amplifier flip-flops, transmission-gate flip-flops), but historically master-slave was the standard implementation because it cleanly avoids the race-around problem with simple latch primitives.