JK Flip-Flop with Preset and Clear Simulator

Fig. 1 — Edge-Triggered JK Flip-FlopInteractive simulation

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What You'll Learn

Recognize the four JK input modes: hold, reset, set, toggle.
Use J=K=1 as a toggle command — the key advantage over SR.
Apply the priority CLR > PRE > clocked JK transition > hold.
Use J = K = 1 to obtain one toggle per rising edge.
Distinguish verified edge-triggered behavior from an unexposed internal implementation.

How It Works

The production component has five inputs: J, K, CLK, PRE, and CLR. With PRE = CLR = 0, a rising clock edge applies the JK characteristic behavior: 00 holds, 01 resets, 10 sets, and 11 toggles Q. Between rising edges, J and K changes do not alter the stored state.

PRE and CLR are separate active-high asynchronous controls. CLR has highest priority and forces Q = 0. If CLR = 0 and PRE = 1, Q is forced to 1. These controls therefore override the clocked JK command.

The circuit contains a single JK primitive rather than a visible pair of master and slave latches. Its observed behavior is edge-triggered, but this topology cannot establish a specific internal hardware construction. Two lights expose Q and Q̅; the oscilloscope exposes CLK and Q.

Truth Table

Rows 1–6 show rising-edge behavior with PRE = CLR = 0. Rows 7–8 show asynchronous controls; their result does not depend on a clock edge.

Inputs					Output
PRE	CLR	J	K	Q_n	Q (next)
0	0	0	0	0	0	Hold preserves Qₙ = 0.
0	0	0	0	1	1	Hold preserves Qₙ = 1.
0	0	0	1	1	0	K resets a stored 1.
0	0	1	0	0	1	J sets a stored 0.
0	0	1	1	0	1	J = K = 1 toggles 0 to 1.
0	0	1	1	1	0	J = K = 1 toggles 1 to 0.
1	0	0	0	0	1	PRE asynchronously forces Q high while CLR is low.
1	1	1	1	1	0	CLR wins when PRE and CLR are both high.

Boolean Expression

Q_{n+1} = J\overline{Q}_n + \overline{K}Q_n

With PRE and CLR low, the characteristic equation determines Q at a rising clock edge.

Q_{n+1}=0 \quad \text{if } CLR=1

Active-high CLR has highest priority and asynchronously forces Q low.

Q_{n+1}=1 \quad \text{if } CLR=0,\ PRE=1

When CLR is low, active-high PRE asynchronously forces Q high.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
CLK=risingCLR=0J=0K=0PRE=0
Expected:Q unchanged
What you'll see:Set both asynchronous controls low before testing. With J = K = 0, a rising edge preserves the current Q state.
2
CLK=risingCLR=0J=1K=0PRE=0
Expected:Q = 1
What you'll see:With J = 1 and K = 0, the next rising edge sets Q to 1.
3
CLK=risingCLR=0J=0K=1PRE=0
Expected:Q = 0
What you'll see:With J = 0 and K = 1, the next rising edge resets Q to 0.
4
CLK=runningCLR=0J=1K=1PRE=0
Expected:Q toggles once per rising edge
What you'll see:With J = K = 1, compare Q after consecutive rising edges. It changes exactly once per edge.
5
CLK=any levelCLR=0PRE=1
Expected:PRE forces Q = 1 asynchronously
What you'll see:Assert PRE while CLR remains low. Q becomes 1 without waiting for CLK.
6
CLK=any levelCLR=1PRE=1
Expected:CLR overrides PRE and forces Q = 0
What you'll see:Assert CLR while PRE is still high. Q becomes 0 because clear has priority.

Components Used

Input / Control Switch

×4

Role: Provides J, K, PRE, and CLR as four independent logic controls.

Clock

×1

Role: Provides the rising edges for synchronous JK state transitions and feeds oscilloscope channel 1.

JK Flip-Flop

×1

Role: Implements hold, reset, set, and toggle transitions plus asynchronous preset and clear.

Output Light

×2

Role: Displays Q and the complementary Q̅ output.

Oscilloscope

×1

Role: Displays CLK on channel 1 and Q on channel 2.

Applications and Design Context

Binary counter cells. A JK flip-flop with J = K = 1 toggles on every active clock edge and therefore divides the frequency of a periodic clock by two. Cascading N toggle stages forms an N-bit ripple counter with an overall division ratio of 2^N.

T flip-flop behavior. Tying J and K together makes a JK flip-flop hold for T = 0 and toggle for T = 1, reproducing the state-transition behavior of a T flip-flop.

State-machine implementation. JK excitation equations can be useful when a design naturally requires set, reset, toggle, and hold transitions. The surrounding combinational logic still has to derive J and K from the required next-state function.

Sequential-logic instruction. Comparing SR, JK, and D devices shows how different input conventions encode the next-state command.

Ripple frequency dividers. Toggle-configured JK stages can form divide-by-2^N chains. Their cumulative clock-to-Q delay makes them asynchronous ripple structures rather than substitutes for a timing-clean synchronous counter.

Frequently Asked Questions

How does JK differ from an SR latch?

At a rising clock edge, J = K = 1 toggles the stored state instead of producing the invalid command associated with an SR latch's simultaneously asserted inputs.

Does this circuit expose a master-slave implementation?

The saved circuit contains one JK_FLIP_FLOP primitive. Its evaluator is rising-edge triggered, but the circuit does not expose internal master and slave latches. The route name is therefore not evidence of a particular transistor- or latch-level implementation.

What is the priority of PRE and CLR?

PRE and CLR are active-high and asynchronous. CLR is evaluated first, so PRE = CLR = 1 deterministically produces Q = 0 in this simulator.

How do I make a T flip-flop from a JK?

With PRE = CLR = 0, tie J and K together. A shared 0 requests hold and a shared 1 requests one toggle on each rising edge.

Which signals are visible?

Two output lights show Q and Q̅. The two-channel oscilloscope shows CLK and Q; Q̅ is not connected to the scope.