CPU Flags Register
A rising-edge flags register stores manually supplied Z, C, N, and V bits when load is enabled, with asynchronous clear. The circuit demonstrates flag storage only; it contains no ALU or logic that derives flags from an operation.
What You'll Learn
- Identify four widely used CPU status flags: Z, N, C, and V.
- Load a four-flag vector on a rising edge when LD = 1.
- Hold the previous flag vector when LD = 0.
- Verify active-high asynchronous clear priority.
- Distinguish storing flags from computing flags in an ALU.
How It Works
The FLAGS_REGISTER has seven inputs in this order: Z_in, C_in, N_in, V_in, LD, CLK, and CLR. Six switches provide the four data flags, load enable, and clear; a clock generator supplies CLK.
CLR is active high and asynchronous. CLR = 1 immediately stores 0000 and overrides other activity. With CLR = 0, a rising clock edge copies Z_in, C_in, N_in, and V_in only when LD = 1. If LD = 0 or no rising edge occurs, the four stored flags hold.
Four lights show the stored outputs in Z, C, N, V order. This topology demonstrates flag storage, not flag generation: there are no ALU or logic gates that derive the input conditions from an arithmetic result.
Boolean Expression
Active-high CLR asynchronously clears all four stored flags.
With CLR low, LD high, and a rising clock edge, the register copies the four independent flag inputs.
Otherwise the previously stored flag vector is retained.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1CLR=1Expected:
Z=C=N=V=0 immediatelyWhat you'll see:Assert CLR. All four output lights turn off immediately. - 2CLK=single rising edgeCLR=0LD=1Z,C,N,V=1,0,1,0Expected:
Stored flags become Z=1, C=0, N=1, V=0What you'll see:Release CLR, set the input vector to Z,C,N,V = 1,0,1,0, assert LD, and apply one rising edge. The Z and N lights turn on. - 3CLK=single rising edgeCLR=0LD=0Z,C,N,V=0,1,0,1Expected:
Stored flags remain Z=1, C=0, N=1, V=0What you'll see:Deassert LD and change every input flag. A rising edge leaves the previously stored Z and N outputs unchanged. - 4CLK=single rising edgeCLR=0LD=1Z,C,N,V=0,1,0,1Expected:
Stored flags become Z=0, C=1, N=0, V=1What you'll see:Set Z,C,N,V = 0,1,0,1, reassert LD, and apply a rising edge. The C and V lights turn on.
Components Used
Applications and Design Context
Processor status storage. ALU-generated conditions can be registered for later branch or arithmetic decisions.
Selective status updates. LD allows a control unit to decide which operation updates the status word.
Initialization and recovery. CLR provides a deterministic all-zero state for the stored flags.
Sequential-logic instruction. Manual inputs isolate and verify storage priority before the register is integrated with flag-generation logic.
Frequently Asked Questions
Does this circuit compute the flag values?
No. Four switches directly drive Z_in, C_in, N_in, and V_in. The circuit contains no ALU, zero detector, sign extraction, carry logic, or overflow logic.
When are new flags stored?
With CLR = 0, LD = 1 causes the four input flags to be copied on a rising CLK edge. LD = 0 leaves the stored vector unchanged.
How does CLR behave?
CLR is active high and asynchronous. It resets Z, C, N, and V to 0 without waiting for a clock edge and has priority over loading.
How are stored flags displayed?
The output order is Z, C, N, V, with one light connected to each output. No oscilloscope is present.
How would this connect to an ALU?
A real datapath could drive the same four input pins from ALU status logic instead of switches. This template isolates the storage and control behavior so that computation is not conflated with registration.