Intermediate Registers, Counters & Memory 8 components

4-Bit Shift Register

This circuit is a 4-bit Serial-In, Parallel-Out (SIPO) Shift Register. Its primary function is to take a stream of data one bit at a time (serially) and store it. Once the data is stored in the register, all four bits can be read simultaneously (in parallel). It essentially converts data from a serial format to a parallel format

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What You'll Learn

Chain 4 D flip-flops as a shift register.
Capture serial input bits into the leftmost flip-flop on each clock edge.
See parallel outputs reflect the 4 most-recent serial bits.
Apply 4-bit shift registers to GPIO expansion and SPI receive.
Calculate the latency for a serial bit to reach a specific position.

How It Works

A 4-bit shift register is four D flip-flops chained: each flip-flop's Q output feeds the next flip-flop's D input. On each clock edge, every bit shifts one position to the right (toward higher bit indices), with the leftmost flip-flop capturing a new serial input bit.

With 4 flip-flops, after 4 clock cycles the entire register has been loaded from the serial input — the first input bit is now in position 3, the most-recent bit is in position 0. This is the serial-in parallel-out (SIPO) configuration.

Applications: - Reassembling serial-bus data into 4-bit words. - Creating 4-cycle delay lines. - Driving 4-output displays from a 1-wire serial bus. - 4-bit pseudo-random generators (with feedback XOR).

The parallel outputs (Q3..Q0) are available continuously — readers see the current state of the register at any time. After 4 clocks of fresh serial input, the parallel output reflects the 4 most-recent input bits in order.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

Serial = 1 Clock = rising 4 times

Expected: Q = 1111

What you'll see: Sustained 1 input filled the register to all 1s after 4 clocks.
2

Serial = 0 Clock = rising 4 times

Expected: Q = 0000

What you'll see: Sustained 0 input cleared the register to all 0s after 4 clocks.
3

Serial = 1, 0, 1, 0 Clock = rising 4 times

Expected: Q = 0101 or 1010

What you'll see: Watch the alternating pattern propagate. After 4 clocks, the register holds the last 4 bits in order.
4

Serial = 1, 0, 0, 0 Clock = rising 4 times

Expected: Q = 0001

What you'll see: Single 1 input followed by 0s — the 1 walked across the register to position 3 and back out, leaving 0001.

Components Used

Shift Register (4-bit)

×1

Output Light

×4

Real-World Applications

74xx165 / 74xx595 ICs. These classic shift register chips expand microcontroller GPIO with 8 output bits via a 3-wire serial interface. The 4-bit version is the conceptual ancestor.

SPI bus receivers. SPI moves data one bit per clock; the receiver's shift register reassembles bytes into 8-bit registers.

LED matrix scanners. Multi-row LED displays use shift registers to load each row's pixel pattern serially before strobing the row.

RFID tag readers. Low-frequency RFID protocols transmit bits serially; readers use shift registers to capture the tag's ID bits.

Test pattern generators. ATE injects test patterns through shift registers to drive specific bit patterns at the device under test.

Frequently Asked Questions

Why right-shift instead of left-shift?

Convention. Some designs shift left (toward higher indices), others right. The behaviour is the same — bits propagate by one position per clock; only the labelling differs.

How long until a bit at the input reaches Q3?

Four clock cycles. Each clock shifts the bit one position. For an N-bit shift register, latency is N cycles.

What if my serial data is faster than the clock?

You'll lose bits — the shift register samples only on its clock edge. Match the clock rate to the data rate, typically using a clock recovered from the data stream itself.

Can I add a parallel-load mode?

Yes — replace each flip-flop's D input with a 2-to-1 MUX that picks between the shift-input (previous bit's Q) and a parallel-load input. A LOAD/SHIFT control signal selects the mode. This gives PISO or universal shift register capability.

How do shift registers relate to FIFOs?

A FIFO is a data buffer with separate read/write pointers. A shift register is a fixed delay line. You can implement a FIFO using shift registers, but real FIFOs are more efficient using RAM with pointer logic.