4-Bit SIPO Shift Register
Four rising-edge D flip-flops form a serial-in, parallel-out register with SI entering Q0 and stored bits advancing toward Q3. Buffered lights and four scope channels expose Q0..Q3; no clear, preset, parallel-load, direction, or serial-output path is connected.
A shared 1 Hz clock advances one serial bit through four rising-edge-triggered D flip-flops. Buffered parallel outputs drive four lights and four inputs of an 8-channel oscilloscope.
What You'll Learn
- Trace the actual FF0 → FF1 → FF2 → FF3 data path in a discrete shift register.
- Apply simultaneous rising-edge sampling to derive the next four-bit state.
- Interpret Q3..Q0 while distinguishing bit order from the left-to-right drawing layout.
- Use the lights and connected oscilloscope traces to verify the stored state.
- Identify functions that are absent from this graph, including reset, parallel load, direction control, and a dedicated serial output.
How It Works
This production circuit implements a four-stage serial-in, parallel-out (SIPO) shift register from four individual D flip-flops. The serial switch feeds FF0's D input. FF0's Q output feeds FF1's D input, FF1 feeds FF2, and FF2 feeds FF3. A single 1 Hz clock drives all four clock inputs, so every stage samples on the same rising edge.
Writing the displayed state as Q3..Q0, one rising edge performs Q3..Q0 ← Q2 Q1 Q0 S. The newly sampled serial bit appears first at Q0. Previously stored bits advance toward Q3, and the former Q3 value leaves the four-bit state. Because the flip-flops sample concurrently, every right-hand value in that assignment is the pre-edge value.
Each Q output then passes through its own buffer. The buffered signal drives one output light and one oscilloscope input, so the lights and four connected traces report the same Q0..Q3 state. The oscilloscope does not receive the clock or serial-input signal in this saved graph, and four of its eight channels are unconnected.
The saved initial state is Q3..Q0 = 0000, with the serial switch and clock LOW. The circuit has no wired clear, preset, parallel-load, direction-control, or serial-output path; those features should not be inferred from packaged shift-register components used in other designs.
Boolean Expression
At every rising clock edge, Q0 captures the serial input S while each higher stage captures the previous state of the stage immediately below it.
Each buffer reproduces its flip-flop output without changing the stored bit.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1Clock=next rising edgeSerial Input=1Starting Q3..Q0=0000 (reload the saved circuit)Expected:
Q3..Q0 = 0001What you'll see:From the saved all-zero state, the first HIGH sample enters Q0; the Q0 light and its buffered scope trace go HIGH. - 2Clock=4 rising edgesSerial Input=1, 0, 1, 0 on four successive rising edgesStarting Q3..Q0=0000 (reload the saved circuit)Expected:
Q3..Q0 = 1010What you'll see:Sampling 1, 0, 1, 0 in that order produces 1010₂ because the first sample has advanced to Q3 and the last sample occupies Q0. - 3Clock=4 rising edgesSerial Input=1Starting Q3..Q0=0000 (reload the saved circuit)Expected:
Q3..Q0 = 1111What you'll see:Four consecutive HIGH samples replace every saved zero, leaving all four outputs HIGH. - 4Clock=4 rising edgesSerial Input=1, then 0 on the next three rising edgesStarting Q3..Q0=0000 (reload the saved circuit)Expected:
Q3..Q0 = 1000What you'll see:A single HIGH sample followed by three LOW samples moves the 1 through 0001 → 0010 → 0100 → 1000.
Components Used
Applications and Design Context
Serial-to-parallel conversion. A SIPO chain accumulates serial samples and exposes the most recent word in parallel. Practical interfaces normally add framing or a separate output latch when downstream logic must see only complete words.
Digital delay lines. A bit captured at Q0 appears at progressively later stages on subsequent rising edges, creating delays measured in whole clock periods.
Output expansion. A controller can send a serial control word to parallel output lines through SIPO logic. This bare chain has no separate output latch, so its visible outputs change while the word is being shifted.
State-history taps. Parallel stage outputs provide delayed versions of a sampled binary stream for sequence detection, filtering, or test-pattern analysis.
Sequential-logic instruction. Building the chain from individual flip-flops makes shared-clock sampling and pre-edge versus post-edge state explicit.
Frequently Asked Questions
How many rising edges does an input bit need to reach Q3?
The first bit is captured in Q0 on the first rising edge and reaches Q3 on the fourth rising edge. After capture, it advances one stage on each of the next three rising edges.
Why does a bit move only one stage per edge?
All four flip-flops sample their D inputs on the same rising edge, using the values that existed immediately before that edge. This simultaneous sampling prevents a new serial bit from racing through multiple stages in one edge.
Does this template include a serial output?
No. The production circuit exposes the four parallel states through buffers, lights, and the oscilloscope, but Q3 is not wired to a separate serial-output component.
Does the circuit have a reset input?
No. The preset and clear inputs on all four D flip-flops are unconnected. Reloading the template restores its saved all-zero state; adding explicit clear wiring would make reset part of the circuit itself.
What do the four buffers do?
The buffers reproduce the four Q values and provide separate branches to the lights and oscilloscope. They do not add storage, change the bit order, or create a parallel-load function.