2-Bit Full-Adder Chain
Two packaged full adders form a 2-bit ripple-carry path with the first carry-in fixed LOW. Three digit displays show both operands and the three-bit result.
What You'll Learn
- Add two unsigned 2-bit operands with cascaded full-adder stages.
- Explain why the least-significant Cin is fixed at 0.
- Trace Cout0 from the low-order stage into Cin1 of the high-order stage.
- Read S0, S1, and final Cout as a three-bit unsigned result.
- Relate ripple-carry structure to width-dependent propagation delay.
How It Works
This production circuit adds two unsigned 2-bit operands, A1A0 and B1B0, with two packaged FULL_ADDER components. Four input switches drive the operand bits, a CONSTANT_ZERO fixes the least-significant carry-in, and three digit displays show A, B, and the three-bit result.
The least-significant stage computes A0 + B0 + 0, producing S0 and Cout0. Cout0 feeds Cin1 of the most-significant stage, which computes A1 + B1 + Cout0 and produces S1 and the final Cout. The result display receives S0, S1, and Cout on bits 0, 1, and 2, respectively, so it reads the unsigned value A + B from 0 through 6.
This is a ripple-carry topology: a carry generated at bit 0 must propagate into bit 1 before the most-significant outputs are final. The packaged full adders expose the stage-level interface without asserting a particular internal gate implementation.
Truth Table
The four switches encode A1A0 and B1B0. These representative rows show the three-bit result Cout S1 S0; the complete function is unsigned A + B over all 16 input combinations.
| Inputs | Output | ||||||
|---|---|---|---|---|---|---|---|
| A1 | A0 | B1 | B0 | Cout | S1 | S0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 + 0 = 0; no stage generates a carry |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 + 1 = 2; bit 0 generates the carry that sets S1 |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 3 + 1 = 4; the carry propagates through both stages |
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 2 + 2 = 4; the high-order stage generates final Cout |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 3 + 3 = 6; all three result bits read 110 |
Boolean Expression
Each full-adder Sum output is the odd-parity function of its two operand bits and carry-in.
Each Cout is high when at least two of the stage's three inputs are high.
The least-significant carry-in is fixed at 0, while the first stage's carry-out becomes the second stage's carry-in.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A0=1A1=0B0=1B1=0Expected:
Cout S1 S0 = 010; result display = 2What you'll see:A1A0 = 01 and B1B0 = 01 generate Cout0 at bit 0; the result display reads binary 010. - 2A0=1A1=1B0=1B1=0Expected:
Cout S1 S0 = 100; result display = 4What you'll see:11 + 01 exercises the longest carry path: bit 0 generates a carry and bit 1 propagates it to final Cout. - 3A0=0A1=1B0=1B1=1Expected:
Cout S1 S0 = 101; result display = 5What you'll see:10 + 11 produces binary 101, showing different values on S0, S1, and Cout. - 4A0=1A1=1B0=1B1=1Expected:
Cout S1 S0 = 110; result display = 6What you'll see:The maximum operands, 11 and 11, produce binary 110, or decimal 6.
Components Used
Applications and Design Context
Small arithmetic datapaths. Cascaded full-adder functions implement addition in simple processors, controllers, and educational CPUs.
Address and index generation. Digital systems repeatedly add small offsets to addresses and counters using the same sum-and-carry relationship.
FPGA and ASIC synthesis. Hardware-description-language additions are mapped to dedicated FPGA carry resources or standard-cell adder structures rather than necessarily preserving these exact packaged symbols.
Multiword arithmetic. Carry information passed between word-sized operations is the software-visible analog of Cout feeding the next Cin.
Timing education. A short ripple chain makes the serial carry dependency easy to inspect before studying carry-lookahead, prefix, or carry-select architectures.
Frequently Asked Questions
Why is the least-significant Cin tied to 0?
The first stage receives a CONSTANT_ZERO at Cin, so it computes A0 + B0 without an incoming carry. Its Cout then supplies the carry-in required by the A1/B1 stage.
Why does Cout0 connect to Cin1?
Cout0 represents the value 2 generated by the least-significant column. Connecting it to Cin1 adds one unit at the next binary weight, so the two stages implement ordinary positional addition.
Do the three digit displays participate in the arithmetic?
No. The input displays show A and B, while the result display receives S0 on bit 0, S1 on bit 1, and the final Cout on bit 2. They visualize the same signals already present in the adder chain.
How can this design be extended to more bits?
Chain additional full adders from least to most significant bit, connect every Cout to the next Cin, and keep only the first Cin fixed at 0. The logical structure scales directly, although worst-case carry delay grows with width.
What is the critical path in this circuit?
A0 = B0 = 1 generates Cout0. If A1 and B1 make the next stage propagate that carry, the final Cout cannot settle until the carry has traversed both components. Wider ripple-carry adders have the same serial dependency.