Single-Bit Equality Detector
An XOR gate forms an internal difference signal and a NOT gate converts it to the visible MATCH output. The light is HIGH for 00 and 11, which is the XNOR equality function.
What You'll Learn
- Use XOR to identify when two single-bit inputs differ.
- Derive XNOR equality by inverting the XOR result.
- Verify the MATCH output for all four input combinations.
- Distinguish the internal DIFF node from the circuit's sole visible output.
- Relate this 1-bit function to multi-bit equality comparators and sampled edge detectors.
How It Works
This circuit compares two single-bit inputs, A and B. The XOR gate first computes an internal difference signal, DIFF = A ⊕ B. DIFF is HIGH when the inputs differ and LOW when they are equal.
A NOT gate then inverts DIFF. Its output drives the circuit's only output lamp, labeled MATCH. Therefore, MATCH = ¬(A ⊕ B) = A ⊙ B: the lamp is HIGH for 00 and 11, and LOW for 01 and 10. This is the XNOR equality function implemented explicitly as XOR followed by NOT.
The schematic does not expose DIFF on a second output lamp. DIFF remains an internal node between the two gates; the visible output is MATCH only. From either switch to the lamp, the signal crosses two gate stages, so the combinational depth is two gate delays, excluding interconnect delay.
The explicit two-stage construction is educationally useful because it demonstrates complementation. In a production library, a direct XNOR cell may implement the same single output with different area, power, and timing characteristics.
Truth Table
MATCH is the XNOR of A and B. The single output is HIGH for equal input pairs and LOW for unequal pairs.
| Inputs | Output | ||
|---|---|---|---|
| A | B | MATCH | |
| 0 | 0 | 1 | Both inputs are LOW; DIFF=0 and MATCH=1. |
| 0 | 1 | 0 | The inputs differ; DIFF=1 and MATCH=0. |
| 1 | 0 | 0 | The inputs differ; DIFF=1 and MATCH=0. |
| 1 | 1 | 1 | Both inputs are HIGH; DIFF=0 and MATCH=1. |
Boolean Expression
The XOR gate creates an internal difference signal that is HIGH exactly when A and B differ.
The NOT gate complements the internal difference signal, so the sole visible MATCH output is HIGH exactly when A and B are equal.
DIFF and MATCH are logical complements. DIFF is an internal node in this schematic, not a second output lamp.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A=0B=0Expected:
MATCH = 1What you'll see:With A=0 and B=0, XOR produces DIFF=0. The NOT gate inverts it, so the MATCH lamp is HIGH. - 2A=1B=0Expected:
MATCH = 0What you'll see:With A=1 and B=0, XOR produces DIFF=1. After inversion, MATCH is LOW. - 3A=1B=1Expected:
MATCH = 1What you'll see:With A=1 and B=1, the inputs are equal again. DIFF returns LOW and MATCH becomes HIGH. - 4A=0B=1Expected:
MATCH = 0What you'll see:With A=0 and B=1, the inputs differ. DIFF is HIGH and the visible MATCH output is LOW.
Components Used
Applications and Design Context
Single-bit equality checks. Control logic can test whether a status bit agrees with an expected mode bit.
Bus equality comparators. Applying the equality function to every bit and AND-reducing the results produces an N-bit all-equal signal used in processor comparisons, cache-tag checks, and protocol logic.
Edge and change detection. XORing a current signal with a registered previous sample produces a difference indication after either transition; this requires storage not present in the displayed circuit.
Parity and error logic. XOR networks summarize whether an odd number of input bits is asserted. Complementing that result selects the opposite parity convention.
Phase comparison. For two periodic digital signals of equal frequency, an XOR node produces a duty cycle related to their phase displacement over the usable range.
Frequently Asked Questions
Why use XOR followed by NOT instead of one XNOR gate?
The two-gate chain makes the identity XNOR = NOT(XOR) visible. If only MATCH is required and the component library provides XNOR, one XNOR gate can replace both gates. If both DIFF and MATCH are required, tapping the XOR node before the inverter provides the two complementary signals from this same chain.
How does this scale to multi-bit equality comparison?
Use one equality result per bit and AND all results to obtain an all-bits-equal signal. Each bit may use either a direct XNOR gate or the XOR-plus-NOT construction shown here.
How is the internal XOR node related to edge detection?
Compare a signal with a delayed, registered copy. The XOR node DIFF then becomes HIGH for one sampling interval after either transition, provided the delay and clocking are designed correctly. In this schematic, DIFF is internal and the visible lamp shows its complement, MATCH.
Is this circuit synchronous or asynchronous?
It is combinational: MATCH follows A and B after the XOR and NOT propagation delays. No clock or storage element is present. To compare current and previous samples, an external flip-flop or register would be required.
Is XOR plus NOT always the most efficient hardware implementation?
No universal transistor count applies. It depends on the semiconductor process, static-CMOS or transmission-gate topology, drive strength, loading, and the characterized standard-cell library. Synthesis should compare available XOR, XNOR, and inverter cells for the actual target.