Intel 4004-Inspired 4-Bit CPU Simulator

Fig. 1 — Intel 4004-Inspired 4-Bit CPUInteractive simulation

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This is a working 4-bit teaching CPU inspired by the Intel 4004—not an emulator, a cycle-accurate replica, or a transistor-level reconstruction. It uses a custom instruction set and transparent simulator blocks to make stored-program execution observable.

What You'll Learn

Trace an instruction through FETCH, DECODE, EXECUTE, and STORE.
Identify the roles of the program counter, instruction register, control unit, accumulator, ALU, flags, and RAM.
Verify program-counter versus instruction-register ownership of the shared RAM address inputs and observe RAM output-enable behavior.
Follow a conditional loop controlled by the zero flag.
Explain how repeated addition computes 4 × 3 without a multiply instruction.
Separate the model's generic 4-bit CPU concepts from claims about the historical Intel 4004.

How It Works

A control unit advances each custom instruction through four visible phases: FETCH, DECODE, EXECUTE, and STORE. The 8-bit program counter selects a byte in unified RAM, the instruction register retains that byte, and the control unit interprets its 4-bit opcode and 4-bit operand fields. The accumulator, ALU, and stored flags form the 4-bit arithmetic datapath.

The program counter and the instruction register's operand outputs share the RAM address inputs. During FETCH, the control unit enables the program counter; during operand access or a jump, it enables the instruction-register address nibble instead. The RAM's eight outputs are high-impedance unless its OE input is active: all eight feed the instruction register, while the low four also feed the ALU's B input. The ALU result has a dedicated connection to the accumulator rather than a shared tri-state data bus. This is a pedagogical organization, not the historical 4004's multiplexed bus protocol.

The bundled custom program multiplies 4 × 3 by repeated addition. RAM locations 0x0B through 0x0F initially hold zero, product, loop counter 3, addend 4, and decrement value 1. Each loop adds 4 to the running product, stores it at 0x0C, decrements the counter at 0x0D, and conditionally jumps while the zero flag is clear. After three iterations, RAM[0x0C] contains 12 and the CPU halts.

The accumulator is reused for both the product and loop counter, so its display changes through intermediate values. The product register's load qualifier is MEM_WR AND NOT A0, where A0 is the instruction operand's least-significant bit. The program stores only to 0x0C and 0x0D, so this one-bit distinction captures product writes but not counter writes. Its display therefore advances cleanly through 0, 4, 8, and 12. This register is lesson instrumentation, not a feature attributed to the historical Intel 4004.

The real Intel 4004 and its MCS-4 system used a different memory organization, instruction set, register structure, stack, bus protocol, and timing. The shared 4-bit datapath and stored-program theme make it an appropriate historical inspiration; they do not make this circuit binary-compatible with Intel 4004 software.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
Action=reload templateClock=stopped
Expected:PC = 0x00, PRODUCT = 0, RAM[0x0C] = 0, RAM[0x0D] = 3
What you'll see:A fresh reload restores both the serialized circuit state and initial RAM image. Product begins at zero, the counter at three, and the constants at four and one.
2
Clock=single-stepObservation=one complete instruction cycle
Expected:The two state lights cycle through 00, 01, 10, and 11 for FETCH, DECODE, EXECUTE, and STORE
What you'll see:Single-stepping exposes the two-bit control-state sequence and lets you record PC, instruction, accumulator, flags, address-source selection, and RAM enables at each phase.
3
Clock=run or single-stepStop at=first store to RAM[0x0C]
Expected:The first product store writes 4 to RAM[0x0C] and the PRODUCT display
What you'll see:On the first product write, MEM_WR is HIGH and operand bit A0 is LOW. That qualifier loads the product register, so RAM[0x0C] and the PRODUCT display both show 4.
4
Clock=run until HALT
Expected:PRODUCT advances 0 -> 4 -> 8 -> 12; the machine then halts
What you'll see:Subsequent stores advance the dedicated display to 8 and 12. When the counter reaches zero, the conditional jump falls through to the final load and HALT.
5
Action=inspect terminal stateHALT=1
Expected:HALT = 1, PC = 0x0B, ACC = 12, PRODUCT = 12, RAM[0x0C] = 12, RAM[0x0D] = 0
What you'll see:The verified terminal state distinguishes architectural and display state: accumulator, product register, and product memory agree at 12; the counter memory is zero; PC has advanced past HALT to 0x0B.

Components Used

Clock

×1

Role: The clock advances the control state and all synchronous storage elements.

Input Switch

×1

Role: The RST switch resets control and selected register state without rewriting RAM.

Output Light

×3

Role: Three lights expose HALT and the encoded control phase.

Control Unit

×1

Role: The control unit decodes the custom instruction and sequences register, memory, ALU, and bus enables.

8-Bit Program Counter

×1

Role: The program counter addresses the current instruction and advances or accepts a branch target.

Logic-HIGH Constant

×1

Role: A fixed HIGH level keeps the RAM chip-select input asserted.

OR Gate

×1

Role: The OR gate combines the control unit's memory-read and RAM-output-enable signals at the RAM OE input.

Logic-LOW Constant

×1

Role: A fixed LOW level holds RAM write-data bits D4 through D7 at zero, so stores write a zero high nibble.

Instruction Register

×1

Role: The instruction register holds the fetched byte while its fields are decoded and executed.

RAM

×1

Role: Unified RAM stores the custom program, constants, loop counter, and running product.

4-Bit ALU

×1

Role: The 4-bit ALU performs the program's AND, ADD, and SUB operations.

4-Bit Register

×2

Role: One 4-bit register is the accumulator; the second is the dedicated product-display register.

Flags Register

×1

Role: The flags register retains the zero condition used by the conditional jump.

Hexadecimal Digit Display

×2

Role: Two hexadecimal displays show the live accumulator and the latched product.

NOT Gate

×1

Role: The inverter complements instruction-operand bit A0 for the product-register load qualifier.

AND Gate

×1

Role: The AND gate qualifies a memory write whose instruction-operand bit A0 is LOW. In the bundled program, that condition identifies the store to product address 0x0C rather than the store to counter address 0x0D.

Applications and Design Context

Computer-architecture education. The model connects program counter, instruction register, control sequencing, datapath, flags, memory, and address selection in one executable system.

Microcode and control-path study. Single-stepping reveals which enables, loads, and operations must occur during each phase of an instruction.

Address-source arbitration. The shared RAM address connections provide a concrete exercise in proving that either the program counter or instruction register owns the driven address, while RAM OE separately controls data visibility.

Machine-code loops. Repeated addition and conditional branching demonstrate how a small instruction set implements an operation it does not provide directly.

Historical comparison. The transparent teaching design offers a controlled basis for comparing generic stored-program concepts with the documented architecture of the 1971 Intel 4004, while preserving the differences between them.

Frequently Asked Questions

Is this an exact Intel 4004 emulator?

No. It is a 4-bit teaching CPU inspired by the 4004. It uses a custom ISA, unified memory, a simplified register and flag model, separate address, RAM-data, and ALU-result paths, and a teaching HALT operation. It must not be used to execute or validate Intel 4004 machine code.

What does the model preserve from its historical inspiration?

It preserves the educationally central ideas of a 4-bit datapath and stored-program execution. The historical 4004's instruction set, program/data organization, index registers, stack, multiplexed interface, and detailed timing are explicitly outside this model.

How does the program multiply without a multiply instruction?

It adds 4 to a running product three times. A counter stored in RAM is decremented after each addition, and a conditional jump repeats the loop until the zero flag indicates completion.

Why are there separate ACC and PRODUCT displays?

The accumulator is time-shared between product arithmetic and loop-counter arithmetic, so its intermediate values are correct but visually noisy. The product register loads when MEM_WR is HIGH and operand bit A0 is LOW. Because this program stores only to 0x0C and 0x0D, that partial decode selects the product writes and produces the readable 0 → 4 → 8 → 12 trace.

Which connections use tri-state output control?

The program counter and instruction register can both drive the RAM address inputs, so the control unit enables only one of them at a time. RAM data outputs are high-impedance when RAM OE is inactive. The 4-bit ALU and register connections here are dedicated wires, not another shared tri-state bus.

What is the difference between toggling RST and reloading the template?

RST clears the control unit, program counter, accumulator, flags, and product register, but it does not restore the RAM image. Reload the template to return program and data memory—including product and loop counter—to their original values.