Modulo-10 Counter Reset-Wiring Diagnostic

Fig. 1 — Modulo-10 Counter Reset-Wiring DiagnosticInteractive simulation

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What You'll Learn

Derive the actual detector equation Q3 · Q1.
Identify every four-bit state for which that partial detector is high.
Explain why tying two ordinary outputs to CLR creates contention rather than OR logic.
Predict counter behavior when CLR resolves to X versus 1.
Specify the single-driver OR-gate repair required for reliable modulo-10 operation.

How It Works

The four-bit COUNTER receives CLK, active-high CLR, and EN = 1. Its Q3..Q0 outputs drive a hexadecimal digit display. Q1 and Q3 also feed a two-input AND, so DETECT = Q3 · Q1. The detector first becomes high at binary 1010 (decimal 10).

The intended modulo-10 idea is to apply DETECT to asynchronous CLR. However, the manual clear switch is connected directly to that same counter input. These are two actively driven outputs, not two inputs of an OR gate. When one drives 0 and the other drives 1, the simulator resolves the shared net to X (contention). The counter clears only for a definite logic 1, so DETECT = 1 with the manual switch at 0 does not produce the intended reset. Conversely, manual clear at 1 conflicts while DETECT = 0.

The only contention-free asserted condition is manual clear = 1 and DETECT = 1. That condition clears the count to 0; DETECT then falls, so CLR returns to X while the manual switch continues to drive 1. Therefore, the saved circuit is best treated as a reset-wiring diagnostic, not as a functioning modulo-10 counter. A correct implementation would OR the two clear requests before CLR.

Boolean Expression

DETECT = Q_3 \cdot Q_1

The two-input AND detector is high whenever Q3 and Q1 are both high. Its first asserted count is decimal 10, but it is also high at 11, 14, and 15 if the counter is allowed to continue.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
Clock=runningManual CLR=0
Expected:The counter follows its native 0..15 sequence instead of a reliable 0..9 sequence
What you'll see:Leave manual CLR at 0 and run the clock. The display can advance beyond 9 because the automatic clear path is not a valid single-driver logic signal.
2
Clock=rising from count 9Manual CLR=0
Expected:DETECT = 1, the shared CLR net resolves to X, and the count is not cleared
What you'll see:Stop at 9 and apply the next rising edge. The count becomes A (1010), DETECT rises, and the CLR net becomes X because the switch still drives 0.
3
Clock=stopped while DETECT = 0Manual CLR=1
Expected:The manual-high and detector-low drivers resolve to X, so clear is not asserted
What you'll see:At a count where DETECT = 0, set manual CLR to 1. The two drivers again disagree, so CLR resolves to X rather than a valid asserted clear.
4
Clock=stopped while Q3 = Q1 = 1Manual CLR=1
Expected:CLR briefly resolves to 1 and clears the counter; DETECT then falls and the still-high manual driver makes CLR return to X
What you'll see:Reach a state with Q3 = Q1 = 1 and then set manual CLR to 1. CLR briefly resolves high and clears the counter. Once Q3 and Q1 fall, DETECT returns low and the still-high manual driver leaves CLR contended at X.

Components Used

Clock

×1

Role: Clocks the four-bit counter and feeds oscilloscope channel 1.

Counter (4-bit)

×1

Role: Counts upward from 0 through 15 on rising edges unless CLR resolves to 1.

Manual Clear Switch

×1

Role: Drives the same CLR input as the detector, creating a multiple-driver net.

AND Gate

×1

Role: Computes DETECT = Q3 · Q1 and feeds both CLR and oscilloscope channel 2.

Logic-1 Constant

×1

Role: Holds the counter enable input at 1.

Digit Display

×1

Role: Shows Q3..Q0 as one hexadecimal digit.

Oscilloscope

×1

Role: Displays CLK and the detector output.

Applications and Design Context

Design-rule verification. The circuit demonstrates why ordinary push-pull outputs must not be shorted to synthesize control logic.

Terminal-count decoding. Partial decode can be valid when the first matched state immediately resets a counter, but only if the reset path itself is correct.

Fault-oriented instruction. Comparing intended modulo behavior with the actual X-resolved net is a useful debugging exercise.

Counter control design. Corrected single-driver reset logic is applicable to decade counters, sequencers, and frequency dividers.

Frequently Asked Questions

Does the saved circuit actually count modulo 10?

Not reliably. The intended detector first asserts at count 10, but its output and the manual clear switch are connected as two ordinary drivers on the same CLR net. Opposite values resolve to X rather than behaving as an OR.

Why does the detector use only Q3 and Q1?

For a counter that resets as soon as 1010 is reached, Q3 AND Q1 is sufficient as a partial decode because 10 is the first reachable state satisfying it. If reset fails, the same detector is also high at 11, 14, and 15.

How should the clear wiring be corrected?

Combine manual clear and terminal-count detection through a real OR gate, then drive CLR from that single output. Alternatively, remove one source if only automatic or only manual clear is required.

Why does an X on CLR fail to clear the counter?

The counter evaluator treats CLR as active only when it resolves to logic 1. A driven-0 plus driven-1 conflict resolves to X, not 1, so neither the detector nor manual switch can clear while the other drives the opposite level.

What can I observe directly?

The digit display receives Q0..Q3. The oscilloscope receives CLK on channel 1 and DETECT on channel 2. No output lights are present.