ROM and Program Counter Demonstration

Fig. 1 — ROM and Program Counter DemonstrationInteractive simulation

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An enabled 8-bit program counter walks through a 256-byte ROM while two saved-HIGH switches control active-low CS and OE. The exact saved state and a reversed set of decorative LED labels make control and bit-order checks essential.

What You'll Learn

Trace the fixed program-counter controls and derive its modulo-256 address sequence.
Apply the ROM's active-low CS and OE truth condition.
Distinguish a high-impedance output from a driven zero even when both leave an output light dark.
Verify the programmed 0x00..0x0F byte sequence and the zero-filled remainder of memory.
Resolve the production graph's reversed decorative LED labels by following authoritative pin IDs and connections.

How It Works

This production circuit combines a 1 Hz clock, an 8-bit program counter, and a 256 × 8 ROM. The HIGH constant drives the counter's INC and OE inputs. The LOW constant drives LD and RST, while all eight parallel-load data inputs are unconnected. Consequently, the counter exposes its current address and increments modulo 256 on each rising clock edge; this graph cannot load or reset it through a user control.

The saved counter address is 0xA7 and the saved clock phase is HIGH. Both ROM control switches are also saved HIGH. The ROM's CS and OE inputs are active LOW, exactly as the canvas labels state and the runtime evaluator implements. Therefore, the initial ROM outputs are eight high-impedance Z values, not a data byte, and all eight output lights are off. Set both CS and OE LOW before attempting to read.

When enabled, the ROM reads address bits A0..A7 as a little-endian binary address. Its saved program contains byte 0x00 at address 0x00, 0x01 at 0x01, and so on through 0x0F at 0x0F. Locations 0x10 through 0xFF are zero-filled. Starting at 0xA7, 89 rising edges are required to wrap the counter to 0x00; the next 15 edges then expose the programmed sequence through 0x0F.

The ROM's D0..D7 outputs connect one-for-one to components led-d0..led-d7. However, the adjacent canvas text is reversed: the led-d0 row is labeled D7 (MSB), while the led-d7 row is labeled D0 (LSB). The evaluator and connections are authoritative, so in this saved graph the top led-d0 light carries D0, the least-significant bit. Read test vectors by ROM signal name rather than by the reversed decorative labels.

A disabled ROM releases the data lines as Z; it does not actively drive eight zeros. The lights look the same for Z and LOW, so the switch settings are essential when interpreting a dark display.

Boolean Expression

A^{+}=(A+1)\bmod 256

With increment and output enable fixed HIGH and load and reset fixed LOW, the program counter advances modulo 256 on each rising clock edge.

\mathrm{ROM}_{\mathrm{out}}(A)=\begin{cases}D(A),&\mathrm{CS}=0\land\mathrm{OE}=0\\Z,&\text{otherwise}\end{cases}

The ROM drives its data pins only when both active-low controls are LOW; otherwise every data pin is high-impedance.

D(A)=\begin{cases}A,&0\le A\le 15\\0,&16\le A\le 255\end{cases}

The programmed bytes equal their addresses from 0x00 through 0x0F. Every remaining location in the saved 256-byte image contains 0x00.

Try It Step-by-Step

Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.

1
CS=1OE=1Program counter=saved address 0xA7
Expected:ROM D7..D0 = ZZZZZZZZ; all eight lights are off
What you'll see:This is the saved control state. Because CS and OE are both HIGH, the ROM releases every output as Z; the dark lights do not mean the ROM is driving 0x00.
2
CS=0OE=1Program counter=saved address 0xA7
Expected:ROM D7..D0 = ZZZZZZZZ; all eight lights are off
What you'll see:Pulling only CS LOW is insufficient. OE remains HIGH, so the ROM still releases all eight data outputs.
3
CLOCK=pause before the next rising edgeCS=0OE=0Program counter=saved address 0xA7
Expected:Address = 0xA7; ROM D7..D0 = 00000000
What you'll see:With both controls LOW and the simulation paused before another rising edge, address 0xA7 reads the zero-filled part of the ROM and drives 0x00.
4
CLOCK=90 rising edges from the saved 0xA7 stateCS=0OE=0
Expected:Address = 0x01; ROM D7..D0 = 00000001
What you'll see:Ninety rising edges advance 0xA7 to 0x01 modulo 256. The ROM drives only D0 HIGH; in this graph that is the top led-d0 row despite its reversed D7 text label.
5
CLOCK=104 rising edges from the saved 0xA7 stateCS=0OE=0
Expected:Address = 0x0F; ROM D7..D0 = 00001111
What you'll see:One hundred four rising edges advance 0xA7 to 0x0F. D3..D0 are HIGH and D7..D4 are LOW; one more edge selects zero-filled address 0x10.

Components Used

Clock

×1

Role: The saved 1 Hz clock drives the program counter's clock input.

HIGH Constant

×1

Role: The HIGH constant holds the program counter's increment and output-enable inputs active.

LOW Constant

×1

Role: The LOW constant holds the program counter's load and reset inputs inactive.

Input Switch

×2

Role: Two switches directly drive the ROM's active-low CS and OE inputs.

Output Light

×8

Role: Eight lights indicate whether each corresponding ROM data output is HIGH; a LOW or high-impedance input leaves a light off.

8-Bit Program Counter

×1

Role: The 8-bit program counter supplies ROM address A0..A7 and increments on rising clock edges.

256 × 8 ROM

×1

Role: The 256 × 8 ROM drives the stored byte at the selected address only while CS and OE are both LOW.

Applications and Design Context

Instruction fetch. A program counter can address read-only instruction storage, although a complete processor also needs control logic for branches, reset, and instruction capture.

Firmware and boot tables. Nonvolatile memory supplies code or constants before writable memory has been initialized.

Lookup tables. An address can select a precomputed function value, waveform sample, character row, or control word.

Shared buses. Active-low chip select and output enable let a memory device release its outputs when another device must drive the same bus.

Memory-test education. This graph makes address order, data-bit significance, enable polarity, and high-impedance behavior independently observable.

Frequently Asked Questions

What does active-low CS or OE mean?

The overbar implied by active-low control means the function is asserted at logic 0. This ROM drives data only for CS = 0 and OE = 0. If either input is 1, all eight outputs are high-impedance.

Why are all the lights off when the template opens?

Both control switches are saved HIGH, so the ROM is deselected and output-disabled. Its data pins are Z, and an output light illuminates only for a driven HIGH input, so all eight lights appear off.

What data is actually programmed into this ROM?

Addresses 0x00 through 0x0F contain the matching byte values 0x00 through 0x0F. Addresses 0x10 through 0xFF contain 0x00 in the saved image.

Why does the illuminated row seem reversed from the binary label?

The authoritative wires connect ROM D0 to led-d0, D1 to led-d1, and so on through D7. The nearby saved canvas text labels those physical rows in the opposite order: the top led-d0 row says D7 and the bottom led-d7 row says D0. Follow the ROM pin IDs and note that the top light is the least-significant data bit in this specific graph.

Is this a combinational or sequential circuit?

The ROM read itself is combinational with respect to address, CS, and OE. The complete template is sequential because a clocked program counter generates the address and advances it over time.

Can this circuit write new data into the ROM?

The running graph has no ROM write input, so its datapath can only read. DigiSim's ROM contents can be edited and assembled as circuit configuration, but that is different from an in-circuit write cycle.