2-Bit Binary Adder
Individual XOR, AND, and OR gates add two 2-bit unsigned operands. The least-significant half-adder stage feeds a full-adder network, and a digit display shows the three-bit result.
What You'll Learn
- Add two two-bit operands with one half-adder stage and one full-adder gate network.
- Trace C0 from the least-significant bit into the most-significant stage.
- Interpret the A, B, and three-bit result digit displays.
- Relate each visible XOR, AND, and OR gate to the adder equations.
- Identify the serial carry path that defines ripple-carry addition.
How It Works
The production circuit adds two two-bit unsigned operands, A1A0 and B1B0, and presents the three-bit result on a digit display. Separate digit displays mirror operands A and B. The arithmetic is implemented with individual XOR, AND, and OR gates rather than packaged adder components.
Bit 0 is a half-adder: - S0 = A0 ⊕ B0 - C0 = A0 · B0
Bit 1 is a full-adder network: - S1 = A1 ⊕ B1 ⊕ C0 - Cout = A1B1 + C0(A1 ⊕ B1)
The result display receives S0 on bit 0, S1 on bit 1, and Cout on bit 2. The maximum input case is 11 + 11 = 110, or 3 + 3 = 6.
Because C0 feeds the bit-1 network, the carry path is serial. This is the defining characteristic of a ripple-carry adder and the reason wider versions eventually require faster carry architectures.
Truth Table
Six representative rows from the 16 possible input combinations show no carry, a local carry, a propagated carry, and the maximum sum.
| Inputs | Output | ||||||
|---|---|---|---|---|---|---|---|
| A1 | A0 | B1 | B0 | Cout | S1 | S0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00 + 00 = 000 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 01 + 01 = 010; bit 0 generates C0 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 10 + 01 = 011; no final carry |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 11 + 01 = 100; carry propagates through bit 1 |
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 10 + 10 = 100; bit 1 generates Cout |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 11 + 11 = 110; maximum unsigned two-bit sum |
Boolean Expression
Bit 0 is a half-adder: XOR generates S0 and AND generates carry C0.
Bit 1 adds A1, B1, and C0; its two XOR gates generate S1.
The two bit-1 carry terms are ORed to produce Cout, which drives result-display bit 2.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A0=1A1=0B0=1B1=0Expected:
Cout S1 S0 = 010 (decimal 2)What you'll see:01 + 01 produces 010. The bit-0 AND gate generates C0, which sets S1. - 2A0=0A1=1B0=0B1=1Expected:
Cout S1 S0 = 100 (decimal 4)What you'll see:10 + 10 produces 100. The bit-1 operands generate Cout directly. - 3A0=1A1=1B0=1B1=0Expected:
Cout S1 S0 = 100 (decimal 4)What you'll see:11 + 01 produces 100. A carry originating at bit 0 propagates through the bit-1 network to Cout. - 4A0=1A1=1B0=1B1=1Expected:
Cout S1 S0 = 110 (decimal 6)What you'll see:11 + 11 produces 110, the maximum result for two unsigned two-bit operands.
Components Used
Applications and Design Context
Small arithmetic datapaths. The same equations implement unsigned addition in compact counters, address generators, and control datapaths.
ALU education and verification. A gate-level view exposes the sum and carry terms that packaged full-adder cells normally hide.
Wider ripple-carry adders. Additional full-adder stages extend the same pattern to larger words when area and simplicity matter more than minimum latency.
FPGA and ASIC synthesis. Hardware-description code for addition is mapped to target-specific carry resources or standard cells that preserve this arithmetic behavior.
Frequently Asked Questions
Why is bit 0 a half adder?
There is no carry input below bit 0 in this circuit, so its third input would be fixed at 0. One XOR and one AND therefore implement the required half-adder function. Bit 1 needs the complete full-adder network because it receives C0.
How can this circuit be extended to four bits?
Add a full-adder gate network for each new bit. Connect each stage's carry-out to the next stage's carry-in, and route the final carry to the new most-significant result bit.
What is the critical path?
The longest structural path in this two-bit schematic passes from the bit-0 AND carry through a bit-1 AND gate and the final OR gate. Actual time delay depends on the selected gates, loading, voltage, and fabrication technology; the logic simulator does not assign a universal nanosecond value.
Can this exact circuit perform subtraction?
Two's-complement subtraction uses A + ¬B + 1. This exact schematic has no controllable carry-in at bit 0, so subtraction requires adding that input—typically by replacing the bit-0 half adder with a full-adder stage—and conditionally inverting B.
How does this differ from a carry-lookahead adder?
This is a ripple-carry implementation: C0 must propagate into the next stage. Carry-lookahead and related architectures derive carry information in parallel and become advantageous as word width and timing pressure increase, at the cost of additional logic and wiring.