2-Bit Binary Adder Circuit Simulator

What You'll Learn

Add two 2-bit numbers using a half-adder + full-adder cascade.
Trace the carry chain through bit 0 and bit 1.
Read the truth table of all 16 input combinations and verify the binary sum.
Recognize the ripple-carry pattern's serial bottleneck.
Apply this slice to wider ALUs by chaining more full-adders.

How It Works

This 2-bit binary adder takes two 2-bit operands (A1 A0 + B1 B0) and produces a 3-bit result (Cout S1 S0). The construction is the textbook ripple-carry pattern: a half-adder for bit 0, a full-adder for bit 1, with bit 0's carry feeding bit 1's carry-in.

For each bit i: Si = Ai ⊕ Bi ⊕ Cini (sum, parity-style); Couti = AiBi + Cini(Ai ⊕ Bi) (carry-out, majority-style). Bit 0's Cin is tied to 0.

The maximum sum is 11 + 11 = 110 (3 + 3 = 6) — three output bits accommodate the overflow.

This is the same ripple-carry pattern that scales to 32 or 64 bits in production CPUs, just narrower. The critical path runs through the carry chain: each bit must wait for the carry from the bit below.

Truth Table

Showing key rows. Full table has 16 input combinations.

Inputs				Output
A1	A0	B1	B0	Cout	S1	S0
0	0	0	0	0	0	0	0 + 0 = 0
0	1	0	1	0	1	0	1 + 1 = 2
1	0	0	1	0	1	1	2 + 1 = 3
1	1	0	1	1	0	0	3 + 1 = 4 (carry)
1	0	1	0	1	0	0	2 + 2 = 4
1	1	1	1	1	1	0	3 + 3 = 6 (max)

Boolean Expression

S_0 = A_0 \oplus B_0,\;\; C_0 = A_0 \cdot B_0

Bit 0 (half-adder).

S_1 = A_1 \oplus B_1 \oplus C_0

Bit 1 sum (full-adder).

C_{out} = A_1 B_1 + C_0(A_1 \oplus B_1)

Bit 1 carry-out — propagates to a third output bit.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

A = 01 B = 01

Expected: Cout S1 S0 = 010

What you'll see: 1 + 1 = 2. Carry from bit 0 makes S1=1.
2

A = 10 B = 10

Expected: Cout S1 S0 = 100

What you'll see: 2 + 2 = 4. Bit 1's full-adder generates the overflow.
3

A = 11 B = 01

Expected: Cout S1 S0 = 100

What you'll see: 3 + 1 = 4. Carry ripples through both stages to Cout.
4

A = 11 B = 11

Expected: Cout S1 S0 = 110

What you'll see: 3 + 3 = 6 — maximum 2-bit sum needs 3 output bits.

Components Used

Real-World Applications

ALU bit-slice. This adder is a 2-bit slice of any wider integer ALU. CPUs build 32- or 64-bit adders from chained slices like this.

Counter logic. Add 1 to a counter each clock edge using exactly this adder structure (with B fixed to 0...01).

Address generators. Memory addressing — base + offset — is wide-integer addition. Same chained-full-adder pattern.

DSP accumulators. Sum of products in DSP loops uses adders for each accumulation step.

Frequently Asked Questions

Why use a half-adder for bit 0?

Bit 0 has no carry-in (nothing below it to carry from), so a full-adder's third input would be wasted. A half-adder is the right size — fewer gates, same function.

How do I extend this to 4 bits?

Chain two more full-adders: bit 2's Cin = bit 1's Cout, bit 3's Cin = bit 2's Cout. Each new bit adds one full-adder to the chain. Same logic, more stages.

What's the worst-case delay?

Two full-adder delays in series (bit 0 must finish before bit 1 can compute). Each full-adder is ~3 gate delays internally, so worst-case ~6 gate delays for 2 bits.

How is subtraction implemented?

Two's complement: invert B, set Cin = 1, add. The same hardware computes A − B. Real ALUs add an XOR row on B controlled by an add/subtract bit.

Is this faster than carry-lookahead?

For 2 bits, no significant difference. Carry-lookahead's advantage shows at 8+ bits, where eliminating the serial carry chain saves gate delays. For 32+ bits, lookahead is essential.