3-Bit Gate-Level Binary Adder
Five XOR gates, five AND gates, and two OR gates form a 3-bit ripple-carry adder without packaged full-adder components. The result display receives the three sum bits and final carry.
What You'll Learn
- Add two three-bit unsigned operands and interpret the four-bit result.
- Distinguish the half-adder gate network at bit 0 from the full-adder networks at bits 1 and 2.
- Trace carry propagation from C_out,0 through C_out,2.
- Map the five XOR, five AND, and two OR gates to the stage equations.
- Explain why the final carry occupies result bit S3.
How It Works
This three-bit binary adder accepts A2A1A0 and B2B1B0, each in the unsigned range 0 through 7, and drives a four-bit digit display with S3S2S1S0. Two additional digit displays mirror the input operands.
The production circuit is constructed from gates, not from three packaged FULL_ADDER components. Bit 0 uses one XOR and one AND as a half adder because C_in,0 is 0. Bits 1 and 2 each use two XOR gates, two AND gates, and one OR gate to implement a full-adder function. The complete non-text logic therefore contains five XOR, five AND, and two OR gates.
For each stage i: - Si = Ai ⊕ Bi ⊕ C_in,i - C_out,i = AiBi + C_in,i(Ai ⊕ Bi)
C_out,0 feeds bit 1, C_out,1 feeds bit 2, and C_out,2 drives S3 on the result display. This serial carry path makes the circuit a ripple-carry adder. The maximum case is 111 + 111 = 1110, or 7 + 7 = 14.
Truth Table
Five representative rows from the 64 possible operand pairs. The inputs are listed as the six physical switches A2, A1, A0, B2, B1, and B0.
| Inputs | Output | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| A2 | A1 | A0 | B2 | B1 | B0 | S3 | S2 | S1 | S0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 000 + 000 = 0000 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 001 + 001 = 0010; carry from bit 0 sets S1 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 011 + 001 = 0100; carry propagates into bit 2 |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 100 + 100 = 1000; bit 2 generates S3 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 111 + 111 = 1110; maximum unsigned three-bit sum |
Boolean Expression
At each stage, the sum bit is the XOR of the two operand bits and the incoming carry; C_in,0 is fixed at 0.
Each higher stage ORs a direct-generate term with a carry-propagate term to form its carry-out.
The final carry from bit 2 drives result-display bit 3, the 8s place.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A0=1A1=0A2=0B0=1B1=0B2=0Expected:
S3 S2 S1 S0 = 0010 (decimal 2)What you'll see:001 + 001 produces 0010. The bit-0 AND gate generates the carry that sets S1. - 2A0=0A1=0A2=1B0=0B1=0B2=1Expected:
S3 S2 S1 S0 = 1000 (decimal 8)What you'll see:100 + 100 produces 1000. The most-significant operand bits generate the final carry directly. - 3A0=1A1=1A2=1B0=1B1=0B2=0Expected:
S3 S2 S1 S0 = 1000 (decimal 8)What you'll see:111 + 001 produces 1000. A carry ripples from bit 0 through both higher stages to S3. - 4A0=1A1=1A2=1B0=1B1=1B2=1Expected:
S3 S2 S1 S0 = 1110 (decimal 14)What you'll see:111 + 111 produces 1110, the maximum result for two unsigned three-bit operands.
Components Used
Applications and Design Context
Compact arithmetic units. Small controllers and teaching processors use the same staged sum-and-carry equations for integer addition.
Address and index generation. Incrementing or adding short offsets uses a narrow adder before the design is scaled to a wider address word.
Arithmetic verification. A gate-level implementation makes carry generation and propagation directly observable for test-vector analysis.
Scalable ripple-carry structure. Additional full-adder stages extend the topology to larger words when a simple, regular implementation is appropriate.
Frequently Asked Questions
Why can a three-bit addition produce a four-bit result?
Each operand can be as large as 111₂ = 7. Their maximum sum is 14, or 1110₂, so the result needs a fourth bit for the final carry.
What determines the worst-case delay?
The circuit is a ripple-carry network. A carry generated at bit 0 may have to pass through the bit-1 and bit-2 carry logic before the most-significant result settles. Physical delay depends on the individual gates and their loads; the important structural fact is the serial dependency across stages.
Does this adder have an overflow condition?
For unsigned arithmetic, S3 is the carry-out that would indicate overflow if the result were restricted to three bits. When all four displayed bits are retained, every unsigned sum from 0 through 14 is represented. Signed two's-complement overflow is a different condition and cannot be inferred from the final carry alone.
Can the circuit be adapted for subtraction?
Two's-complement subtraction uses A + ¬B + 1. This production circuit has a half-adder LSB with no controllable Cin, so supporting subtraction requires a bit-0 carry input as well as conditional inversion of all B bits.