2-to-1 Multiplexer
One select bit chooses whether output Y follows D0 or D1. The packaged component implements Y = (NOT S AND D0) OR (S AND D1).
What You'll Learn
- Use a single select bit to route one of two data inputs to the output.
- Read the 2-to-1 MUX truth table — output follows D0 when S=0, D1 when S=1.
- Write the SOP Boolean expression: Y = ¬S·D0 + S·D1.
- Recognize MUXes inside ALUs, FPGAs, and bus arbiters.
- Understand that any 2ⁿ-row truth table can be realized by a 2ⁿ-to-1 MUX.
How It Works
A multiplexer (MUX) is a digital data selector: it routes one of N inputs to an output according to a select signal. The 2-to-1 MUX is the smallest case, with two data inputs D0 and D1, one select line S, and one output Y.
When S = 0, Y follows D0; when S = 1, Y follows D1. Changing S determines which data path reaches the output.
The Boolean expression is Y = (¬S · D0) + (S · D1). The first AND term is enabled when S=0 and selects D0; the second is enabled when S=1 and selects D1. This is the classic Sum-of-Products form.
A 2-to-1 MUX needs ⌈log₂(2)⌉ = 1 select bit. A 4-to-1 MUX needs two select bits to address its four inputs, and an 8-to-1 MUX needs three. The number of select bits therefore grows logarithmically with the number of data inputs. For a power-of-two N, a balanced tree of 2-to-1 MUXes contains N−1 selector cells and log₂N selection levels; only the control width and tree depth, not the total hardware, scale logarithmically.
MUXes are also fundamental primitives for synthesis: any 2ⁿ-row truth table can be implemented as a 2ⁿ-to-1 MUX with the input variables as select lines and the truth-table output values wired to the data inputs. The same selection principle provides a conceptual model for an FPGA LUT: a k-input LUT stores 2^k configuration bits and selects one, like a 2^k-to-1 MUX. Its physical implementation is device-specific.
Truth Table
S selects which data input passes through. Showing all 8 (S, D0, D1) combinations.
| Inputs | Output | |||
|---|---|---|---|---|
| S | D0 | D1 | Y | |
| 0 | 0 | 0 | 0 | S=0 → Y=D0=0 |
| 0 | 0 | 1 | 0 | S=0 → Y=D0=0 (D1 ignored) |
| 0 | 1 | 0 | 1 | S=0 → Y=D0=1 |
| 0 | 1 | 1 | 1 | |
| 1 | 0 | 0 | 0 | S=1 → Y=D1=0 (D0 ignored) |
| 1 | 0 | 1 | 1 | S=1 → Y=D1=1 |
| 1 | 1 | 0 | 0 | |
| 1 | 1 | 1 | 1 | |
Boolean Expression
Sum-of-products form. Each AND term "selects" one data input based on S.
Ternary operator notation — same logic, conditional read.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1D0=1D1=0S=0Expected:
Y = 1What you'll see:S=0 selects D0. Output follows D0 (=1). D1 is ignored. - 2D0=0D1=1S=0Expected:
Y = 0What you'll see:S=0 still selects D0. D1's value doesn't affect Y. - 3D0=1D1=0S=1Expected:
Y = 0What you'll see:Flipping S to 1 switches the steering — now D1 is selected. D0 is ignored. - 4D0=0D1=1S=1Expected:
Y = 1What you'll see:S=1, D1=1 — output is 1. The MUX has transparently routed the chosen input through.
Components Used
Applications and Design Context
ALU operation selection. A CPU's ALU uses MUXes to choose between adder, shifter, and logic-unit outputs based on the instruction's opcode.
Bus arbitration. Multiple sources compete for a shared bus; a MUX selects which source's data reaches the destination based on a grant signal.
FPGA lookup tables. A k-input LUT stores 2^k configuration bits and selects one with its k logical inputs. It is conceptually a 2^k-to-1 selection network—for example, 16-to-1 for four inputs or 64-to-1 for six—although the physical implementation is device-specific.
Conditional selection in processor datapaths. Hardware can implement "if condition, then x = a, else x = b" with a MUX controlled by the condition. Some instruction-set architectures expose conditional-move or select instructions, while others use branches or instruction sequences; CMOV is not a universal mnemonic.
Network packet routing. Switches use MUXes to direct each incoming packet to the appropriate outgoing port based on routing-table lookup.
Frequently Asked Questions
Is a 2-to-1 MUX the same as an if/else?
Functionally, yes. The conditional expression "if S then Y = D1 else Y = D0" describes exactly what a 2-to-1 MUX computes. Hardware synthesis tools commonly map conditional HDL expressions to MUX structures when appropriate for the target technology.
How does the MUX scale to more inputs?
An N-to-1 MUX needs ⌈log₂N⌉ select bits. A 4-to-1 has 2 select bits, an 8-to-1 has 3, a 16-to-1 has 4. Build wide MUXes from a tree of 2-to-1s if your library doesn't have them as primitives.
What's the difference between a MUX and a tri-state bus?
A MUX always actively drives its output (Y is 0 or 1). A tri-state bus has multiple drivers, only one enabled at a time; the others float. MUXes are simpler to verify (no contention possible); tri-state saves wiring across long distances.
Can I build a MUX from NAND gates only?
Yes — NAND is universal. A 2-to-1 MUX needs 4 NAND2 gates: two for the AND terms, one for the NAND-implementation of OR, and one inverter for ¬S. Layouts often use transmission gates for fewer transistors.
Why is a MUX called a 'data selector'?
Because it selects which data input is routed to the output, controlled by the select line. "Multiplexer" emphasizes the multi-input nature; "data selector" emphasizes the routing decision.