4-Bit Code Detector (1010)
NOT and AND gates implement the minterm that asserts the output only for input 1010. The visible code and purely combinational output make this a decoder example, not a secure authentication mechanism.
What You'll Learn
- Derive the minterm that recognizes the fixed input word 1010.
- Explain why required-zero inputs are inverted before conjunction.
- Trace the two-level AND tree from pair-valid signals to UNLOCK.
- Verify from the complete truth table that exactly one input vector is accepted.
- Compare the propagation paths of direct and inverted input literals.
- Distinguish fixed combinational decoding from secure credential verification.
How It Works
This circuit is a 4-bit fixed-word detector presented as a digital lock. The four switches, read from top to bottom, are I3, I2, I1, and I0. The accepted word is 1010: I3 and I1 must be HIGH, while I2 and I0 must be LOW.
The two required-zero signals pass through NOT gates, producing I̅2 and I̅0. One first-stage AND gate evaluates I3 · I̅2, and the other evaluates I1 · I̅0. A final AND gate combines those pair results. Therefore, UNLOCK = I3 · I̅2 · I1 · I̅0, which is HIGH for exactly one of the 16 possible input vectors.
The circuit does not compare the input against stored constants with XNOR gates; it implements the one accepted word directly as a minterm. A path from I3 or I1 crosses two AND gates. A path from I2 or I0 crosses one NOT gate and two AND gates, so the worst-case combinational depth is three gate delays, excluding interconnect delay.
The visible code and purely combinational output make this useful for studying decoding and active-high/active-low conditions, but unsuitable as a real security mechanism.
Truth Table
UNLOCK implements the minterm I3·I̅2·I1·I̅0. It is HIGH only for 1010; every other row violates at least one required literal.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| I3 | I2 | I1 | I0 | UNLOCK | |
| 0 | 0 | 0 | 0 | 0 | I3 and I1 are LOW; the word is rejected. |
| 0 | 0 | 0 | 1 | 0 | I3 and I1 are LOW, and I0 has the wrong polarity. |
| 0 | 0 | 1 | 0 | 0 | I3 is LOW; the word is rejected. |
| 0 | 0 | 1 | 1 | 0 | I3 is LOW, and I0 has the wrong polarity. |
| 0 | 1 | 0 | 0 | 0 | I3 and I1 are LOW, and I2 has the wrong polarity. |
| 0 | 1 | 0 | 1 | 0 | I3 and I1 are LOW; I2 and I0 also have the wrong polarity. |
| 0 | 1 | 1 | 0 | 0 | I3 is LOW, and I2 has the wrong polarity. |
| 0 | 1 | 1 | 1 | 0 | I3 is LOW; I2 and I0 also have the wrong polarity. |
| 1 | 0 | 0 | 0 | 0 | I1 is LOW; the word is rejected. |
| 1 | 0 | 0 | 1 | 0 | I1 is LOW, and I0 has the wrong polarity. |
| 1 | 0 | 1 | 0 | 1 | All four required literals are true; UNLOCK is HIGH. |
| 1 | 0 | 1 | 1 | 0 | Only I0 has the wrong polarity. |
| 1 | 1 | 0 | 0 | 0 | I1 is LOW, and I2 has the wrong polarity. |
| 1 | 1 | 0 | 1 | 0 | I1 is LOW; I2 and I0 also have the wrong polarity. |
| 1 | 1 | 1 | 0 | 0 | Only I2 has the wrong polarity. |
| 1 | 1 | 1 | 1 | 0 | I2 and I0 have the wrong polarity. |
Boolean Expression
The two required-zero inputs pass through NOT gates, while the required-one inputs remain noninverted.
Two first-stage AND gates check the upper and lower pairs; the final AND gate asserts UNLOCK only when both pairs match 1010.
MISMATCH is the complement of UNLOCK. By De Morgan's law, it is HIGH whenever at least one required literal is false.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1I3=0I2=0I1=0I0=0Expected:
UNLOCK = 0What you'll see:With 0000 applied, the inverted inputs match their required LOW levels, but I3 and I1 remain LOW, so UNLOCK is LOW. - 2I3=1I2=0I1=1I0=0Expected:
UNLOCK = 1What you'll see:For 1010, all four literals I3, I̅2, I1, and I̅0 are HIGH. Both pair checks pass and UNLOCK becomes HIGH. - 3I3=1I2=0I1=1I0=1Expected:
UNLOCK = 0What you'll see:Changing only I0 to 1 drives I̅0 LOW, causing the lower pair check and UNLOCK to go LOW. - 4I3=0I2=1I1=0I0=1Expected:
UNLOCK = 0What you'll see:The complement word 0101 violates all four required literals and is rejected. - 5I3=1I2=1I1=1I0=0Expected:
UNLOCK = 0What you'll see:Changing only I2 to 1 drives I̅2 LOW, causing the upper pair check and UNLOCK to go LOW.
Components Used
Applications and Design Context
Address decoding. A fixed minterm can assert chip select when an address bus equals one assigned binary pattern.
Instruction and control decoding. Control logic recognizes selected opcode or mode-field combinations by ANDing the required true and complemented bits.
Configuration interlocks. Equipment can enable an operation only when a small set of switches occupies one approved state.
Test-pattern recognition. Production tests may detect a known binary stimulus and use the resulting signal to trigger a measurement or capture event.
Educational lock models. Naming the decoded minterm UNLOCK provides an intuitive demonstration of polarity, inversion, conjunction, and the limitations of visible hardwired codes.
Frequently Asked Questions
Why are only I2 and I0 inverted?
The stored word requires I2=0 and I0=0. Inverting those signals produces HIGH match literals when the switches are LOW. I3 and I1 must be HIGH, so they feed the AND network directly.
Why does the circuit use three AND gates?
The simulator uses 2-input gates. The first two AND gates evaluate I3·I̅2 and I1·I̅0; the third gate combines the pair results. This balanced structure realizes the required 4-input conjunction.
How can the detector support another or a longer code?
For another hardwired word, use each input directly when the required bit is 1 and invert it when the required bit is 0, then AND all literals. If the reference word must be changeable, use one XNOR comparator per bit followed by an AND reduction.
How should a wrong-attempt counter be added?
Sample MISMATCH = ¬UNLOCK with a synchronous submit pulse and increment a registered counter on each submitted mismatch. Do not count the free-running combinational level: an unchanged incorrect word would otherwise be counted repeatedly, and propagation glitches could create false attempts.
Is this circuit suitable for real access control?
No. The required word is visible in the wiring, and there is no protected credential storage, attempt timing, or cryptographic protocol. This is an instructional fixed-word detector, not a secure authentication system.
How does this circuit relate to an address decoder?
The Boolean structure is the same as a one-word address decoder: both assert an output for exactly one input minterm. The surrounding system determines whether that output is called UNLOCK, chip select, instruction select, or something else.