Three-Stage T Flip-Flop Frequency Divider
Three rising-edge T flip-flops form an asynchronous ripple divider with divide-by-2, divide-by-4, and divide-by-8 outputs. An active-HIGH asynchronous reset clears every stage, and the scope displays digital state traces rather than physical timing.
What You'll Learn
- Explain why a T flip-flop with T = 1 divides its clock frequency by 2.
- Trace the actual three-stage cascade from the source clock through Q1, Q2, and Q3.
- Relate the three observed outputs to divide-by-2, divide-by-4, and divide-by-8 ratios.
- Distinguish a ripple-clocked divider from a synchronous counter.
- Verify the effect of an active-high asynchronous reset on every stage.
How It Works
The production circuit contains three positive-edge-triggered T flip-flops, not one. A logic-1 constant drives every T input. The source clock drives stage 1; stage 1 Q clocks stage 2; and stage 2 Q clocks stage 3. With T fixed at 1, each stage toggles on every rising edge at its own clock input.
Consequently, stage 1 Q has one-half the source-clock frequency, stage 2 Q has one-quarter, and stage 3 Q has one-eighth. The topology is asynchronous, or ripple-clocked, because only the first stage receives the source clock.
The RESET switch is wired to the active-high asynchronous clear pin of all three flip-flops. RESET = 1 forces every stored Q state to 0 independently of the clock. After RESET returns to 0, the next relevant rising edges restart the divide chain.
The 8-channel oscilloscope observes the source clock followed by the three Q outputs. It does not measure analog delay, rise time, or metastability; it presents the simulator's digital logic states.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1Clock=runningRESET=1Expected:
All three Q outputs are forced to 0What you'll see:Hold RESET at 1 and inspect channels 2 through 4. Every Q trace remains at 0 even while the source clock continues. - 2Clock=running at 2 HzRESET=0Expected:
The three Q traces divide the clock by 2, 4, and 8What you'll see:Release RESET to 0. Channel 2 toggles on source-clock rising edges; channels 3 and 4 toggle on rising edges of the preceding Q signal. - 3Clock=observe 8 rising edgesRESET=0Expected:
Each successive Q trace changes at half the rate of the preceding stageWhat you'll see:Across eight source-clock rising edges, compare transition counts rather than assuming the stages share one edge: each downstream trace changes half as often. - 4Clock=runningRESET=0 → 1 → 0Expected:
All Q outputs clear immediately and division resumes after RESET returns to 0What you'll see:Assert RESET at any clock phase. The three stored outputs clear without waiting for an edge; release RESET to begin a new sequence.
Components Used
Applications and Design Context
Power-of-two clock division. Toggle stages provide slower timing references when a ripple-clocked architecture is acceptable.
Binary-state demonstrations. Parallel observation of successive Q outputs makes the relationship between stored bits and frequency division explicit.
Prescalers and timer front ends. Divider stages can reduce an event rate before subsequent counting or measurement logic. Practical implementations must account for device timing and clock-domain requirements that this ideal digital model does not simulate.
Sequential-logic education. The circuit gives a direct comparison between one source clock and three derived waveforms while keeping T permanently asserted.
Frequently Asked Questions
Why is divide-by-2 so common?
A toggle stage changes state once per active input edge, so one complete Q period requires two input edges. Cascading stages therefore produces the exact power-of-two ratios 2, 4, and 8 used in this circuit.
How do I divide by 4? By 8?
This production circuit already contains three cascaded stages. The first stage is clocked by the source clock, the second by the first Q output, and the third by the second Q output.
What does the RESET switch do?
It initializes all three stored Q states to 0. Because RESET is connected directly to each T flip-flop's asynchronous clear input, it does not wait for a clock edge.
Which signals are visible on the oscilloscope?
The source clock and the three stored Q outputs occupy oscilloscope channels 1 through 4. The remaining four channels are intentionally unconnected.
Why is this called a ripple divider?
It is a ripple divider: each stage's Q output is the next stage's clock. The stages therefore do not share one clock edge. A synchronous counter instead clocks every storage element from the same source and computes the next state with combinational logic.