Complementary Clock-Driven Lights
A clock drives one light directly and a second through a NOT gate, producing complementary logic levels. The inverter changes polarity but does not divide frequency, and the circuit contains no storage element.
What You'll Learn
- Trace the clock fan-out to the direct light and inverter input.
- Write Direct = CLK and Complement = ¬CLK.
- Verify that exactly one light is on for either stable clock level.
- Distinguish polarity inversion from divide-by-two stateful behavior.
- Recognize the safety functions omitted from a conceptual crossing-light demo.
How It Works
The production circuit contains one CLOCK, one NOT gate, and two output lights. CLK fans out directly to the upper light and to the inverter input. The inverter output drives the lower light.
The two equations are Direct = CLK and Complement = ¬CLK. For a stable low clock level, Direct is off and Complement is on. For a stable high level, Direct is on and Complement is off. As the clock oscillates, the two indicators exchange states every time CLK changes.
There is no T flip-flop, counter, or other storage element in this graph. The inverter does not divide the clock. Ignoring propagation delay, each light repeats at the same cycle frequency as CLK; the two waveforms differ only in polarity.
The alternating visual resembles a railroad-crossing pair, but it is only a logic demonstration. A real crossing controller needs train detection, activation and clearance timing, lamp diagnostics, fail-safe behavior, power supervision, and certified output hardware.
Truth Table
The graph is combinational with respect to the current clock level: one light follows CLK and the other displays ¬CLK.
| Inputs | Output | ||
|---|---|---|---|
| CLK | Direct | Complement | |
| 0 | 0 | 1 | CLK low — direct light off, complementary light on. |
| 1 | 1 | 0 | CLK high — direct light on, complementary light off. |
Boolean Expression
The upper light is connected directly to the clock output.
The lower light is driven by a NOT gate, so it always shows the complement of the clock in stable states.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1CLK=0Expected:
Direct = 0, Complement = 1What you'll see:At CLK = 0, the direct branch is low and the inverter drives the complementary branch high. - 2CLK=1Expected:
Direct = 1, Complement = 0What you'll see:At CLK = 1, the direct branch is high and the inverter drives the complementary branch low. - 3Clock=runningExpected:
The two lights alternate as complementary clock phasesWhat you'll see:While CLK runs, the lights swap on every level transition. There is no frequency division or stored state.
Components Used
Applications and Design Context
Complementary indicators. Two indicators can visualize a binary phase and its complement.
Polarity conversion. An inverter creates an active-low control from an active-high clock or status signal.
Two-phase observation. Direct and inverted test points help demonstrate phase opposition and propagation delay.
Clock diagnostics. Complementary outputs can make a slow clock's alternating levels easy to observe during teaching or bench testing.
Warning-light concept demonstrations. The pattern illustrates alternating presentation, while real warning systems add independent control, monitoring, and fail-safe circuitry.
Frequently Asked Questions
Why are the two lights complementary?
One light receives CLK directly and the other receives ¬CLK. When the clock changes level, their stable on/off states exchange.
How can I make the alternation slower?
Adjust the clock period or insert a genuine divider such as a toggle flip-flop or counter. The NOT gate only changes polarity; it does not divide frequency.
Can this circuit create a three-light sequence?
A stateful three-phase sequence requires storage, such as a counter or finite-state machine, plus decoding logic. A clock and one inverter can produce only two complementary levels.
Is this a one-bit counter or sequential circuit?
No. The production graph contains no T flip-flop, latch, or counter. Both outputs are combinational functions of the current clock level, so neither retains independent state.
What happens if the clock glitches?
A pulse or glitch on CLK appears directly on one branch and, after inverter delay in physical hardware, with opposite polarity on the other. A deployed warning system needs a qualified clock and suitable fault handling.