Unidirectional Register Transfer
Register A captures a 4-bit switch word, and Register B can capture A's outputs on a later shared clock edge. Independent load controls and a shared asynchronous reset are provided; there is no shared bus, arbitration, or reverse transfer.
What You'll Learn
- Load a four-bit external word into Register A on a rising edge.
- Transfer Register A's stored word into Register B on a later rising edge.
- Use independent load enables with a shared clock.
- Verify the active-high asynchronous reset shared by both registers.
- Distinguish this direct unidirectional path from a tri-state shared-bus architecture.
How It Works
Four switches drive D0..D3 of Register A. Both four-bit registers share one clock but have independent active-high load inputs. On a rising edge with LOAD A = 1, Register A captures the external word. Its Q0..Q3 outputs are wired directly to Register B's D0..D3 inputs. On a rising edge with LOAD B = 1, Register B captures that source word.
A shared active-high asynchronous RESET drives both registers. RESET = 1 forces both stored words to 0000 regardless of clock or load. It must be returned to 0 before either load operation can succeed.
Register B drives the digit display. The oscilloscope uses five of eight channels: CLK, LOAD A, LOAD B, A.Q0, and B.Q0. The circuit is a unidirectional two-stage register path; it has no tri-state buffers, shared bus, arbitration, or B-to-A transfer.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1Clock=any levelRESET=1Expected:
Register A = 0000, Register B = 0000, display = 0What you'll see:Assert RESET. Both stored words clear asynchronously, and the display reports 0. - 2Clock=single rising edgeD3..D0=1010LOAD A=1LOAD B=0RESET=0Expected:
Register A = 1010 while Register B remains 0000What you'll see:Release RESET, set D3..D0 = 1010, assert LOAD A only, and apply one rising edge. A stores 1010; B still stores 0000. - 3Clock=single rising edgeLOAD A=0LOAD B=1RESET=0Expected:
Register B = 1010 and the digit display shows AWhat you'll see:Deassert LOAD A, assert LOAD B, and apply one rising edge. B captures A = 1010, so its hexadecimal display shows A. - 4Clock=single rising edgeD3..D0=0101LOAD A=1LOAD B=0RESET=0Expected:
Register A = 0101 while Register B and its display remain at 1010What you'll see:Load 0101 into A without enabling B. The A.Q0 scope trace changes, while B.Q0 and the displayed destination word retain 1010.
Components Used
Applications and Design Context
Pipeline staging. One register can hold a source word while a following register accepts it under a separate enable.
Peripheral data capture. A stable source register can feed a destination register that samples only when its subsystem is ready.
Micro-operation instruction. The circuit demonstrates register-transfer notation such as B ← A without implying a full register file or bus fabric.
Synchronous datapaths. Independent enables allow adjacent state elements to advance or hold on the same clock.
Frequently Asked Questions
Is this transfer implemented with a shared bus?
It is a direct, one-way four-wire path from Register A's Q outputs to Register B's D inputs. The production circuit contains no tri-state buffers, shared bidirectional bus, or reverse B-to-A path.
What do the two load controls do?
LOAD A enables Register A to capture the four external D inputs on a rising edge. LOAD B independently enables Register B to capture Register A's current four-bit output on a rising edge.
How does RESET behave?
RESET is connected to the active-high asynchronous clear input of both registers. While RESET = 1, both words are forced to 0000 and cannot be loaded.
Which signals are observable?
The destination word drives one hexadecimal digit display. The oscilloscope receives CLK, LOAD A, LOAD B, Register A Q0, and Register B Q0 on channels 1 through 5.
Does Register B follow Register A continuously?
No. Register B changes only on a rising edge at which LOAD B = 1. At all other times it retains its previously stored word, even if Register A or the external data switches change.