3-Bit Up/Down Counter
A synchronous 3-bit counter that counts up or down depending on a direction input. T flip-flops toggle under combinational steering logic so all bits change on the same clock edge.
This synchronous 3-bit counter advances or decrements modulo 8 according to one direction input. All T flip-flops update on the same rising clock edge.
What You'll Learn
- Trace the complete modulo-8 sequence in both directions.
- Derive toggle-enable equations for Q0, Q1, and Q2.
- Explain how the direction input selects HIGH-bit or LOW-bit terminal conditions.
- Contrast simultaneous synchronous updates with ripple-counter propagation.
- Predict wraparound and a direction change at a specified clock edge.
How It Works
Q0 is the least-significant bit and toggles on every rising edge because T0 is tied HIGH. The Up input U selects the conditions for the higher stages. During upward counting, Q1 toggles when Q0 = 1, and Q2 toggles when Q1Q0 = 11. During downward counting, Q1 toggles when Q0 = 0, and Q2 toggles when Q1Q0 = 00.
The steering equations are T1 = UQ0 + U̅Q̅0 and T2 = UQ1Q0 + U̅Q̅1Q̅0. Each T flip-flop applies Q_i(next) = Q_i ⊕ T_i. The circuit implements the two product terms for each higher toggle input with AND gates and combines them with OR gates.
Because all three storage elements share the same clock, outputs change as one synchronous state transition rather than rippling from Q0 upward. With U = 1, the sequence is 000 → 001 → … → 111 → 000. With U = 0, it is 000 → 111 → … → 001 → 000. The direction line should be stable around the active clock edge in physical hardware, just like any synchronous control input.
Truth Table
This complete state-transition table uses U = 1 for up and U = 0 for down. Current and next counter states are written Q2 Q1 Q0, from most-significant to least-significant bit.
| Inputs | Output | ||||||
|---|---|---|---|---|---|---|---|
| Up | Current Q2 | Current Q1 | Current Q0 | Next Q2 | Next Q1 | Next Q0 | |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | Down-counting from 0 wraps to 7. |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | |
| 0 | 0 | 1 | 1 | 0 | 1 | 0 | |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | |
| 0 | 1 | 0 | 1 | 1 | 0 | 0 | |
| 0 | 1 | 1 | 0 | 1 | 0 | 1 | |
| 0 | 1 | 1 | 1 | 1 | 1 | 0 | Down-counting from 7 produces 6. |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | Up-counting from 0 produces 1. |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | |
| 1 | 0 | 1 | 0 | 0 | 1 | 1 | |
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | The transition 3 → 4 toggles all three bits synchronously. |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | Up-counting from 7 wraps to 0. |
Boolean Expression
The least-significant stage toggles on every active clock edge.
Q1 toggles at an odd state while counting up and at an even state while counting down.
Q2 toggles at an all-ones lower field when counting up and at an all-zeros lower field when counting down.
Each T input determines whether its stored bit holds or complements on the next edge.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1Clock=one rising edgeInitial state=reload template at 000Up=1Expected:
Q2 Q1 Q0 = 001What you'll see:From the defined zero state, one upward edge toggles only Q0 and produces decimal 1. - 2Clock=eight rising edgesInitial state=reload template at 000Up=1Expected:
The sequence reaches 111 and wraps to 000 on the eighth rising edgeWhat you'll see:Eight upward edges traverse all eight states and return to zero, demonstrating modulo-8 wraparound. - 3Clock=one rising edgeInitial state=reload template at 000Up=0Expected:
Q2 Q1 Q0 = 111What you'll see:One downward edge from zero wraps directly to decimal 7, so all three outputs become HIGH together. - 4Clock=one additional rising edgeUp=1 for three edges, then 0Expected:
The counter reaches 011 upward, then reverses to 010 on the next edgeWhat you'll see:Direction affects the combinational T inputs before the edge. Reversing U at state 011 makes the next state 010 instead of 100.
Components Used
Applications and Design Context
Bidirectional address generation. Memory, image, and signal-processing systems scan buffers forward or backward.
Position and motion control. Up/down event counts track incremental encoders when separate direction logic determines the sign of movement.
Timers and remaining-count displays. The same architecture supports elapsed and countdown modes.
Digital tuning and menu controls. Increment/decrement interfaces update bounded or wrapping numeric state.
Synchronous-control education. The circuit demonstrates how combinational next-state logic drives a bank of flip-flops on one clock.
Frequently Asked Questions
Why is Q0's T input tied HIGH?
The least-significant bit changes on every count, regardless of direction. A T flip-flop toggles whenever T = 1, so a constant HIGH implements that rule directly.
Why do higher bits use different conditions for up and down?
An upward carry reaches the next bit when all lower bits are 1. A downward borrow reaches it when all lower bits are 0. The direction input selects between those two terminal conditions.
What makes this counter synchronous?
Every T flip-flop receives the same clock. The AND–OR network computes toggle enables in advance, and all stored bits update together at the active edge.
What happens if Up changes near a clock edge?
In real hardware, violating the direction input's setup or hold requirement can make the captured transition unreliable. Synchronous controls must be stable around the active edge or be synchronized appropriately.
How would this design scale to N bits?
Bit i toggles during upward counting when every lower bit is 1, and during downward counting when every lower bit is 0. Wider AND trees generate those conditions, often with optimized lookahead structures for speed.