4-Bit Clocked Register
A 4-bit register captures D3..D0 on a rising edge when Load is HIGH and otherwise holds its state. Active-HIGH clear is asynchronous; the scope shows clock and load but does not measure physical timing parameters.
What You'll Learn
- Store a four-bit value on an enabled rising clock edge.
- Distinguish LOAD = 1 capture from LOAD = 0 hold.
- Verify that CLEAR is active high and asynchronous.
- Read Q3..Q0 from the four output indicators.
- Interpret the CLK and LOAD traces without inferring unmodeled analog timing.
How It Works
The four data switches drive D0..D3 of one four-bit REGISTER. With CLEAR = 0, the register examines LOAD on each rising clock edge. LOAD = 1 captures all four D bits; LOAD = 0 preserves the current Q3..Q0 word.
CLEAR is an active-high asynchronous control. CLEAR = 1 forces all four stored bits to 0 independently of the clock and prevents a simultaneous load from taking effect. Return CLEAR to 0 before testing clocked capture.
Four lights expose Q0..Q3. The oscilloscope receives the clock and LOAD signals only, which is useful for confirming when an enabled rising edge occurs but does not directly plot the data word. This simulator verifies digital transition rules, not physical timing parameters.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1CLEAR=1Expected:
Q3..Q0 = 0000 immediatelyWhat you'll see:Set CLEAR to 1. All four Q lights turn off immediately, regardless of clock and LOAD. - 2CLEAR=0Clock=single rising edgeD3..D0=1010LOAD=1Expected:
Q3..Q0 = 1010 after the rising edgeWhat you'll see:Release CLEAR, present 1010, and assert LOAD. The next rising edge stores 1010. - 3CLEAR=0Clock=single rising edgeD3..D0=0101LOAD=0Expected:
Q3..Q0 remains 1010What you'll see:Deassert LOAD, change D to 0101, and allow another rising edge. Q remains 1010. - 4CLEAR=0Clock=risingD3..D0=0101LOAD=1Expected:
Q3..Q0 = 0101 after the rising edgeWhat you'll see:Assert LOAD while D remains 0101. The next rising edge replaces the stored word with 0101.
Components Used
Applications and Design Context
Datapath state. Parallel registers retain intermediate words between operations.
Pipeline enables. LOAD can represent a valid or advance condition, allowing a stage to hold during a stall.
Configuration storage. A decoded write strobe can act as LOAD for a small control register.
Input sampling. Multiple logic lines that satisfy the register's setup and hold requirements can be captured as one word on a designated clock edge. Asynchronous inputs require separate clock-domain-crossing treatment.
Frequently Asked Questions
Does this register load on every clock edge?
The register captures D3..D0 only on a rising clock edge for which LOAD = 1. If LOAD = 0, the same clock edge leaves the stored word unchanged.
How does CLEAR behave?
CLEAR is active high and asynchronous. It forces Q3..Q0 to 0000 without waiting for a clock edge and overrides LOAD while asserted.
Which signals are visible?
Four output lights show Q0 through Q3. The two oscilloscope channels show CLK and LOAD; neither data inputs nor Q outputs are connected to the scope.
Does the waveform view measure physical timing limits?
No. The model performs ideal digital state transitions. It does not characterize setup time, hold time, clock-to-Q delay, or analog behavior.
How does a register differ from a counter?
A register stores an externally supplied word when enabled. A counter instead computes its own next numeric state. Both retain state, but their next-state functions differ.