3-to-8 Decoder
A 3-bit input code asserts exactly one of eight active-HIGH outputs. Each output corresponds to one three-variable minterm.
What You'll Learn
- Convert a 3-bit binary code into one of 8 one-hot output lines.
- Read the 3-to-8 decoder truth table — 8 input rows, 8 outputs, exactly one high per row.
- Write each output as a unique 3-input minterm of A2, A1, A0.
- See how decoders scale: 3 inputs → 8 outputs; 8 inputs → 256 outputs; etc.
- Apply for memory row select, chip select, and instruction-class decode.
How It Works
A 3-to-8 decoder takes a 3-bit input (A2 A1 A0) and asserts exactly one of eight outputs (Y0–Y7) — the one whose index equals the binary value of the input.
For example, A2A1A0 = 101 (decimal 5) asserts Y5 = 1; all others stay at 0. Each output Yi = the i-th 3-variable minterm: Y0 = ¬A2¬A1¬A0, Y1 = ¬A2¬A1·A0, ..., Y7 = A2A1A0.
The number of outputs grows exponentially with the number of input bits. Because each output has its own minterm, the number of minterm paths grows linearly with the output count. This one-of-many mapping makes decoders useful for address decoding in memory systems where an address code must select one storage resource.
A direct gate-level 3-to-8 decoder can use eight three-input AND gates plus three NOT gates shared across the minterms. Each output path then passes through any required input inverter and one AND stage. Physical delay and area still depend on the cell library, fan-in implementation, load, and routing; this packaged component does not model them.
Truth Table
Each of the 8 input codes asserts exactly one output. The output index equals the binary value of the input.
| Inputs | Output | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| A2 | A1 | A0 | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Code 0 → Y0 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Code 1 → Y1 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Code 2 → Y2 |
| 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Code 3 → Y3 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Code 4 → Y4 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Code 5 → Y5 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Code 6 → Y6 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Code 7 → Y7 |
Boolean Expression
Each output is the i-th 3-variable minterm. With 3 inputs there are 2³ = 8 minterms — one per output.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A0=0A1=0A2=0Expected:
Y0=1, others=0What you'll see:Code 0 → Y0. The 'home' position of any binary decoder. - 2A0=1A1=1A2=0Expected:
Y3=1, others=0What you'll see:Code 011 = 3 → Y3 lights. The active output index matches the binary input value. - 3A0=0A1=0A2=1Expected:
Y4=1, others=0What you'll see:Code 100 = 4 → Y4. Flipping just the high bit jumps to the upper half. - 4A0=1A1=1A2=1Expected:
Y7=1, others=0What you'll see:All 1s → Y7, the last output. Walk through 0–7 to see the active line shift one step at a time.
Components Used
Applications and Design Context
Memory address row decoding. A small RAM with 8 rows uses a 3-to-8 decoder driven by 3 address bits to select the row to read or write.
8-output chip-select. A microcontroller addressing 8 peripheral chips uses a 3-to-8 decoder driven by 3 high-order address bits.
Display digit selection. Multiplexed 8-digit displays cycle through digit-strobe lines via a 3-to-8 decoder.
Octal-to-decimal logic. Older octal computer systems used 3-to-8 decoders to convert internal octal codes to one-hot indicator lines.
Instruction class decode. A CPU's opcode field's top 3 bits often select one of 8 instruction classes via a 3-to-8 decoder, with each class running its own micro-sequencer.
Frequently Asked Questions
Why are decoders called 'one-hot' generators?
Because exactly one output is hot (=1) at a time. The output pattern is one-hot encoding — easy to fan out to per-row enables in memory or per-action signals in a state machine.
How does this differ from a 1-to-8 DEMUX?
A DEMUX takes a data input D and routes it to one selected output — D's value flows to the active output. A decoder has no D — its active output is always 1. A DEMUX with D held high behaves identically to a decoder.
Can a 3-to-8 decoder have an enable?
Yes — most production decoders include an enable input that gates all outputs to 0 when low. This allows cascading: a master decoder selects which sub-decoder is enabled, and the sub-decoder asserts the final one-hot.
How is this implemented in a memory chip?
Memory chips use much wider decoders, such as a decoder with 14 inputs and 16,384 outputs for a 16K-word memory. Implementations commonly use hierarchical predecoding: partition the address bits into groups, decode each group, and combine the predecoded lines. This limits the fan-in of individual stages and can improve loading, layout, and critical-path behavior; it does not guarantee a lower total gate count.
What if the input bus has glitches during transition?
Decoder outputs may briefly assert wrong lines as bits flip. For systems where glitches matter (e.g., write-enable fan-out), the output is registered through a flip-flop, sampling only when the address bus is stable.