What You'll Learn

  • Read and write the NOT gate's 2-row truth table.
  • Recognise the inverter symbol (a triangle followed by a small circle/bubble).
  • Convert active-low signals to active-high using a single inverter.
  • Apply De Morgan's laws to convert AND/OR networks using inversion.
  • Understand that NOT is the cheapest CMOS gate (2 transistors).

How It Works

The NOT gate, or inverter, is the simplest logic gate: one input, one output, and the rule "output is the opposite of input." Wire a switch into a NOT gate and the output light turns on when the switch is off, and turns off when the switch is on. Boolean expression: Y = ¬A (or A̅, or NOT A).

With only two possible inputs (0 or 1), the truth table has exactly two rows. NOT is sometimes called the "complement" or "inversion" function because it produces the logical complement of its input.

Despite its simplicity, NOT is fundamental: every Boolean expression can be transformed using De Morgan's laws if you can negate signals, and the universal NAND/NOR gates are essentially AND/OR followed by NOT. In CMOS silicon, a NOT gate is just two transistors — one PMOS and one NMOS in series — making it the cheapest gate to fabricate.

NOT is also where signal integrity matters most. A long chain of inverters introduces propagation delay (each adds ~50 ps to ~1 ns depending on technology), and inverter chains are sometimes used as delay lines for timing trim.

Truth Table

NOT has only one input, so just two rows. Output is always the opposite of input.

Inputs Output
A Y
0 1 Input 0 → output 1 (inverted)
1 0 Input 1 → output 0 (inverted)

Boolean Expression

Y=AY = \overline{A}

Standard form using overline notation.

Y=¬AY = \lnot A

Formal logic notation using the negation symbol.

Y=1AY = 1 \oplus A

NOT can be implemented as XOR with a constant 1 — useful when only XOR gates are available.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

  1. 1
    A = 0
    Expected: Y = 1
    What you'll see: Switch off, output light on. NOT inverts: 0 becomes 1.
  2. 2
    A = 1
    Expected: Y = 0
    What you'll see: Switch on, output light off. NOT inverts: 1 becomes 0. The light is the **inverse** of the switch.

Components Used

Real-World Applications

Active-low signal conversion. Many digital signals are "active low" — chip-select, write-enable, reset — meaning they're considered active when at logic 0. To use them with active-high logic, an inverter does the conversion in one gate.

Building NAND from AND. A NAND gate is just AND followed by NOT. The same goes for NOR (OR followed by NOT). Inverters are everywhere — they're how the universal gates are constructed.

Driver / buffer chains. A chain of inverters in series doesn't change logic but does buffer the signal — driving heavier loads (long wires, many gate inputs) with stronger drive strength. An even number of inverters in series equals a buffer.

Clock distribution. Inverters in clock trees both reshape the clock waveform and provide delay tuning. A whole chip's clock skew is managed by carefully placed inverter buffers.

De Morgan transformations in synthesis. Logic-synthesis tools constantly apply De Morgan's laws: NOT(A AND B) = NOT(A) OR NOT(B). Inverters are the primary tool for these transformations.

Frequently Asked Questions

Why does the NOT gate symbol have a small circle on the output?
The little circle (called a "bubble") universally indicates inversion in logic schematics. NAND gates are AND-with-bubble; NOR gates are OR-with-bubble. The bubble means "invert this signal."
Is a buffer the same as a NOT gate?
No — a buffer outputs the same logic value as its input (Y = A) but provides drive strength. A NOT gate inverts (Y = ¬A). Two NOT gates in series form a buffer.
How is NOT implemented in CMOS?
Two transistors — a PMOS pull-up (turns on when input is 0) and an NMOS pull-down (turns on when input is 1) — wired in a complementary fashion. It's the smallest, fastest gate in the CMOS family.
What's the propagation delay of an inverter?
Depends on technology. In a modern 7nm process, ~5–20 ps. In older 130nm CMOS, ~80 ps. In educational simulators, propagation is treated as instantaneous.
Can I implement any logic function using only NOT gates?
No. NOT alone is not universal — you need at least NAND or NOR (both of which include NOT internally). NOT is necessary in any complete logic family but not sufficient on its own.

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