4-Bit Johnson Counter
Four D flip-flops share one clock, with the final complementary output fed back to the first stage. From the simulator's defined 0000 start, the intended Johnson sequence contains eight states; no separate reset control is connected.
A Johnson counter, also called a twisted-ring counter, shifts state through a register while feeding the inverted last output back to the first stage.
What You'll Learn
- Construct a twisted-ring feedback path with the final complementary output.
- Trace the complete eight-state sequence from 0000 back to 0000.
- Explain why an N-stage Johnson counter has 2N states in its intended cycle.
- Compare Johnson, one-hot ring, binary, and ripple counter structures.
- Recognize the need for defined startup or reset behavior in physical sequential circuits.
How It Works
Four positive-edge-triggered D flip-flops share one clock. Q0 feeds D1, Q1 feeds D2, and Q2 feeds D3. The complementary output of the final stage feeds D0, creating the twist that distinguishes this circuit from an ordinary ring counter.
Starting from the simulator's known 0000 state and writing outputs as Q0 Q1 Q2 Q3, successive rising edges produce 1000, 1100, 1110, 1111, 0111, 0011, 0001, and then 0000. A run of 1s first fills the register; a run of 0s then empties it. The intended cycle therefore contains 2N = 8 states for N = 4 flip-flops.
All stages receive the same clock, so this is a synchronous sequence rather than a ripple counter. Simple combinational decoders can recognize individual Johnson states because each intended state has a structured boundary between runs of equal bits. A physical implementation normally includes reset or startup logic to guarantee entry into the desired cycle; this template begins from a defined all-zero simulator state and has no separate reset switch.
Truth Table
This transition table covers the intended eight-state cycle. Vectors use the displayed Q0 Q1 Q2 Q3 order and show the state immediately after the next rising edge.
| Inputs | Output | |||||||
|---|---|---|---|---|---|---|---|---|
| Current Q0 | Current Q1 | Current Q2 | Current Q3 | Next Q0 | Next Q1 | Next Q2 | Next Q3 | |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Inverted Q3 inserts the first 1 at Q0. |
| 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | The run of 1s expands to Q1. |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | The run of 1s expands to Q2. |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | The register becomes all ones. |
| 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | Inverted Q3 is now 0, beginning the emptying phase. |
| 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | The run of 0s expands to Q1. |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | Only Q3 remains HIGH. |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | The final 1 shifts out and the cycle returns to 0000. |
Boolean Expression
The complementary output of the last stage is fed back into Q0 on the next edge.
Q0 shifts into Q1.
Q1 shifts into Q2.
Q2 shifts into Q3.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1Clock=0Initial state=reload templateExpected:
Q0 Q1 Q2 Q3 = 0000What you'll see:Reloading establishes the known all-zero state used as the start of the intended cycle. - 2Clock=first rising edgeExpected:
Q0 Q1 Q2 Q3 = 1000What you'll see:Because Q3 is 0, its complementary output is 1 and the first edge loads Q0. - 3Clock=four rising edges from 0000Expected:
After four rising edges, Q0 Q1 Q2 Q3 = 1111What you'll see:Four edges fill the register with 1s in the order Q0, Q1, Q2, Q3. - 4Clock=eight rising edges from 0000Expected:
After eight rising edges, Q0 Q1 Q2 Q3 returns to 0000What you'll see:Four additional edges shift 0s into the same positions and complete the eight-state period.
Components Used
Applications and Design Context
Multi-phase timing. Decoded Johnson states can provide a repeating set of phase enables for controllers and timing generators.
Sequence control. The eight-state cycle offers more states than a one-hot ring with the same four flip-flops while retaining regular state patterns.
Frequency division. The complete state cycle repeats every eight input clocks, and individual outputs exhibit divided periodic waveforms.
Scanner and channel control. Decoded states can step through a fixed schedule of rows, channels, or operations.
Digital-logic education. Comparing ring, Johnson, binary, and ripple counters highlights different state encodings and feedback structures.
Frequently Asked Questions
Why is this called a twisted-ring counter?
The register forms a ring, but the complementary output of the last flip-flop—not its direct Q output—feeds the first D input. That inversion is the twist.
How many states does an N-bit Johnson counter have?
Its intended fill-and-empty cycle contains 2N states. Four flip-flops therefore produce eight intended states.
Why does this circuit not need a preset bit like the ring counter?
From 0000, inverted feedback supplies a 1 automatically. An ordinary ring counter feeds back 0 from 0000 and would remain locked there without a seeded 1.
Can a Johnson counter enter states outside the intended cycle?
Yes. Four flip-flops have 16 possible states, while the intended Johnson cycle uses eight. Practical hardware uses reset or self-correction logic to guarantee the required startup sequence.
Is a Johnson counter asynchronous?
No. All four D flip-flops in this circuit share the same clock and update synchronously. Its feedback topology does not make it a ripple counter.