Register Load and Clock Selection
A 2-to-1 multiplexer selects an automatic or manual clock for a 4-bit register used here as a 2-bit demonstration. Load controls capture, clear acts asynchronously, and the scope shows D0, D1, selected clock, and load rather than Q.
What You'll Learn
- Select correctly between automatic and manual clock sources.
- Apply LOAD = 1 for capture and LOAD = 0 for hold.
- Generate a manual rising edge by toggling the manual clock from 0 to 1.
- Verify active-high asynchronous clear behavior.
- Explain why only the lower two bits of the four-bit primitive are observable.
How It Works
The production circuit uses a four-bit REGISTER primitive as a two-bit demonstration. D0 and D1 are driven by switches and Q0 and Q1 drive two lights. D2 and D3 are disconnected, so the simulator's input convention samples them as 0 on a load; Q2 and Q3 are not connected to indicators.
A 2-to-1 multiplexer supplies the register clock. CLOCK SELECT = 0 chooses the automatic 0.5 Hz clock. CLOCK SELECT = 1 chooses the manual switch; a manual rising edge requires changing that switch from 0 to 1.
With CLEAR = 0, a selected-clock rising edge captures D1D0 only if LOAD = 1. LOAD = 0 holds the existing state. CLEAR = 1 asynchronously forces all register bits to 0 and overrides loading. The oscilloscope shows D0, D1, selected CLK, and LOAD—not Q.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1CLEAR=1Expected:
Q1Q0 = 00 immediatelyWhat you'll see:Set CLEAR to 1. Both displayed Q bits turn off immediately; clock selection and LOAD do not alter the cleared state. - 2Automatic clock=next rising edgeCLEAR=0CLOCK SELECT=0D1D0=10LOAD=1Expected:
Q1Q0 = 10 after the next automatic-clock rising edgeWhat you'll see:Release CLEAR, select the automatic clock, set D1D0 = 10, and assert LOAD. The next rising edge stores 10. - 3Automatic clock=runningCLEAR=0CLOCK SELECT=0LOAD=0Expected:
Q1Q0 remains 10 while LOAD = 0What you'll see:Set LOAD to 0 and change D1D0 while the automatic clock runs. The Q lights retain 10. - 4CLEAR=0CLOCK SELECT=1D1D0=01LOAD=1Manual clock=0 → 1Expected:
Q1Q0 = 01 after the manual clock changes from 0 to 1What you'll see:Select the manual clock, start it at 0, set D1D0 = 01 with LOAD = 1, then toggle the manual clock to 1. The lights update to 01.
Components Used
Applications and Design Context
Laboratory clock selection. A slow automatic source and a manual step source make state transitions observable at different rates. This circuit uses an ordinary logic MUX; changing SELECT while its inputs differ can itself create a transition. Hardware clock networks normally use a characterized glitch-free clock MUX or a clock-enable scheme.
Enabled state registers. Load control allows a register to advance only when a valid-data or write-enable condition is present.
Pipeline hold controls. Deasserting an enable can preserve a stage's state while the surrounding clock continues.
Laboratory instruction. The two-bit view keeps the relationship among data, selected clock, load, clear, and stored outputs directly observable.
Frequently Asked Questions
How is the clock source selected?
A 2-to-1 multiplexer selects either the automatic clock (CLOCK SELECT = 0) or the manual switch (CLOCK SELECT = 1). Its output drives the register clock and oscilloscope channel 3.
When is new data captured?
LOAD is active high and synchronous. The register captures D1D0 only on a rising edge of the selected clock. With LOAD = 0, clock edges leave the stored state unchanged.
Why does the page demonstrate only two bits with a four-bit register?
The physical primitive is four bits wide, but only D0, D1, Q0, and Q1 are connected. D2 and D3 are unwired and sample as 0 when a load occurs; their Q outputs are not displayed.
Is CLEAR synchronous?
CLEAR is an active-high asynchronous input. It forces all four internal bits to 0 immediately and must return to 0 before a load can succeed.
Which signals does the oscilloscope show?
Channels 1 and 2 show D0 and D1, channel 3 shows the selected clock, and channel 4 shows LOAD. The two Q outputs are represented by lights rather than oscilloscope channels.