4-Bit Right-Shift Register
Fixed LOW direction and shift/load controls select right-shift mode: SI enters Q3, stored bits move toward Q0, and SO reflects Q0. The scope exposes clock, SI, every Q stage, and SO.
What You'll Learn
- Trace right-shift movement Q3 → Q2 → Q1 → Q0.
- Relate chronological SI order to the resulting Q3..Q0 word.
- Verify that DIR and S/L are both fixed at 0.
- Interpret all seven connected oscilloscope channels.
- Recognize that SO duplicates Q0 for this fixed direction.
How It Works
The four-bit SHIFT_REGISTER has inputs SI, CLK, DIR, S/L, and D0..D3. One logic-0 constant drives both DIR and S/L. Under the production evaluator, DIR = 0 selects right shift and S/L = 0 selects serial-shift mode. Thus, on every rising clock edge, Q0 ← Q1, Q1 ← Q2, Q2 ← Q3, and Q3 ← SI. SO reflects Q0 in this mode.
The oscilloscope receives CLK, SI, Q0, Q1, Q2, Q3, and SO. This makes every internal stage visible; the circuit is not limited to observing one serial output. Q0 and SO are deliberately redundant in the fixed direction.
A serial bit presented before an edge first appears at Q3. It reaches Q0 after three subsequent shifts. Test vectors must therefore state both the chronological SI order and the Q3..Q0 display order; treating SI as if it entered Q0 would reverse the result.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1Clock=4 rising edgesSI=0, 0, 0, 0Expected:
Q3Q2Q1Q0 = 0000 and SO = 0What you'll see:Hold SI at 0 for four rising edges to flush any saved state. All parallel taps and SO become 0. - 2Clock=4 rising edgesSI=0, 1, 0, 1Expected:
Q3Q2Q1Q0 = 1010 and SO = Q0 = 0What you'll see:Apply SI chronologically as 0, 1, 0, 1 on four successive rising edges. Because each new bit enters Q3, the final Q3..Q0 word is 1010. - 3Clock=1 rising edgeSI=1Expected:
Q3Q2Q1Q0 = 1101 and SO = Q0 = 1What you'll see:Apply SI = 1 for one more rising edge. The old 1010 shifts toward Q0, producing 1101; SO follows the new Q0 = 1. - 4Clock=4 rising edgesSI=0, 0, 0, 0Expected:
Q3Q2Q1Q0 returns to 0000 after four zero bitsWhat you'll see:Apply four zero bits. Each edge moves the remaining ones one stage toward Q0 until the register and SO are all 0.
Components Used
Applications and Design Context
Serial-to-parallel staging. Successive bits can be inspected as one four-bit state after four edges.
Digital delay lines. A serial bit advances one stage per clock and emerges at the terminal stage after a fixed number of shifts.
Sequence analysis. Exposing every Q tap helps verify bit order in serial protocols and test patterns.
Shift-register instruction. Fixed direction and mode make this circuit a controlled demonstration of one precise transition rule.
Frequently Asked Questions
Which way does data move in this saved circuit?
DIR is tied to logic 0. In the implemented evaluator, that selects right shift: SI enters Q3, then data advances Q3 → Q2 → Q1 → Q0. The SO output reflects Q0.
Can this template perform a parallel load?
S/L is also tied to logic 0, which selects serial-shift mode. The D0..D3 parallel inputs are disconnected and are ignored while S/L remains low.
Which oscilloscope channels are connected?
CLK, SI, Q0, Q1, Q2, Q3, and SO occupy channels 1 through 7. Channel 8 is unconnected. Because SO = Q0 in right-shift mode, channels 3 and 7 show the same logic state.
Is the circuit strictly serial-in/serial-out?
It exposes both the parallel taps Q0..Q3 and the serial output SO on the oscilloscope. Functionally, the circuit can therefore be studied as SIPO and as SISO even though the route slug says SISO.
Does the scope measure propagation delay?
No analog delay is modeled. State changes occur according to ideal rising-edge digital semantics; the scope is for logic sequences, not clock-to-Q timing measurement.