Active-High SR Latch
Set and Reset switches control one packaged active-HIGH SR latch with Q and complementary outputs. The 00 input holds state, 10 sets, 01 resets, and 11 is represented as unknown by this digital model.
What You'll Learn
- Identify the SR latch as the simplest memory element.
- Recognize the four input combinations: Set, Reset, Hold, Forbidden.
- Trace the cross-coupled feedback that creates bistable storage.
- Distinguish level-sensitive latches from edge-triggered flip-flops.
- Apply SR latches to debounce, arbitration, and SRAM cells.
How It Works
This circuit connects Set (S) and Reset (R) switches to one packaged active-high SR latch. Two lamps display Q and ¬Q. The component stores one bit: S=1,R=0 sets Q; S=0,R=1 resets Q; and S=0,R=0 retains the previously stored value.
A conceptual NOR implementation uses two cross-coupled gates. Q feeds one input of the gate that produces ¬Q, and ¬Q feeds one input of the gate that produces Q. This positive feedback creates two stable legal states. For legal inputs, Qnext = S + ¬R·Q.
S=R=1 is invalid for this active-high latch. DigiSim displays both outputs as unknown (X) while the condition is present. A physical NOR latch instead forces both outputs LOW during simultaneous assertion and can resolve unpredictably when the inputs are released together, because real propagation delays are never exactly equal.
An SR latch is level-sensitive and asynchronous: a set or reset level can change its stored state immediately. Clocked latches and edge-triggered flip-flops add control over when a state change may occur.
Truth Table
Qprev is the previously stored value. The table enumerates legal inputs; S=R=1 is excluded because DigiSim displays both outputs as unknown (X), which is not a binary value.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| S | R | Qprev | Qnext | ¬Qnext | |
| 0 | 0 | 0 | 0 | 1 | Hold the stored 0 state. |
| 0 | 0 | 1 | 1 | 0 | Hold the stored 1 state. |
| 0 | 1 | 0 | 0 | 1 | Reset forces Q LOW from a stored 0 state. |
| 0 | 1 | 1 | 0 | 1 | Reset forces Q LOW from a stored 1 state. |
| 1 | 0 | 0 | 1 | 0 | Set forces Q HIGH from a stored 0 state. |
| 1 | 0 | 1 | 1 | 0 | Set forces Q HIGH from a stored 1 state. |
Boolean Expression
For legal input combinations, S sets Q, R clears Q, and S=R=0 preserves the previous state.
In a conceptual cross-coupled NOR implementation, each output feeds one input of the opposite NOR gate.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1R=0S=1Expected:
Q = 1What you'll see:Set the latch — Q goes high. Now release S back to 0 and Q stays high. The latch remembers. - 2R=0S=0Expected:
Q unchangedWhat you'll see:After setting, both inputs low → latch holds. Q stays at whatever it was. This is the memory function. - 3R=1S=0Expected:
Q = 0What you'll see:Reset — Q drops to 0. Release R and Q stays at 0. Latch now in the reset state, awaiting next Set. - 4R=1S=1Expected:
Q = X, ¬Q = X (invalid input condition)What you'll see:With S and R both HIGH, DigiSim marks Q and ¬Q as unknown. Avoid this combination; physical release behavior is timing-dependent.
Components Used
Applications and Design Context
Static memory principles. A conventional 6-transistor SRAM cell stores one bit in two cross-coupled inverters and uses two access transistors for the complementary bit lines. It is bistable like an SR latch, although its read/write interface is not the two-switch interface shown here.
Asynchronous control state. Carefully designed set/reset paths can retain an event or fault indication until a separate clear condition occurs. Designers must prevent simultaneous assertion or define explicit priority.
Mechanical-switch debouncing. An SPDT switch can drive mutually exclusive set and reset inputs so that contact bounce on one throw does not create repeated output transitions.
Reset and alarm capture. A set-dominant or reset-dominant latch can preserve a brief event for later observation, but its priority behavior must be explicitly defined; the basic component here has no priority for S=R=1.
Arbitration foundations. Cross-coupled storage appears in arbiters and synchronizers, but real metastability handling requires analog timing analysis beyond this idealized digital latch.
Frequently Asked Questions
Why is S=R=1 called forbidden?
For a physical active-high NOR latch, both asserted inputs force both gate outputs LOW and release can resolve according to relative path timing. The DigiSim SR_LATCH component represents the invalid condition by driving both displayed outputs to X. Real designs prevent S and R from being asserted together.
What's the difference between SR latch and SR flip-flop?
An SR latch is asynchronous (output changes immediately when inputs change). An SR flip-flop is clocked (output changes only on a clock edge). Flip-flops have an extra clock input that gates when the latch can change.
How does SRAM use this?
Each SRAM cell is two cross-coupled CMOS inverters (effectively an SR latch's two NORs become two inverters when one input is fixed at 0). Two access transistors connect the cell to the bit lines for read/write. The bistable storage holds the bit between accesses.
Can I make an SR latch from NAND gates?
Yes — two cross-coupled NANDs make an active-low SR latch, often labeled S̄ R̄. The behavior is mirror-imaged: S̄=0 sets Q=1; R̄=0 resets Q=0; S̄=R̄=1 holds; S̄=R̄=0 is forbidden. Same circuit, inverted polarities.
What about latches with no forbidden state?
A gated D latch, introduced in the related sequential-logic templates, prevents the SR forbidden input combination by deriving mutually exclusive set and reset requests from one data input and an enable. The two internal requests cannot both be asserted for a binary D value.