Rising-Edge D Flip-Flop
The flip-flop samples D on rising clock edges and exposes Q and its complement. Active-HIGH preset and clear act asynchronously, with clear taking priority in this simulator model.
What You'll Learn
- Distinguish edge-triggered (D flip-flop) from level-sensitive (D latch) behavior.
- Apply the exact priority CLR > PRE > rising-edge D capture > hold.
- Distinguish synchronous D capture from asynchronous preset and clear.
- Correlate the Q light with the clock and Q oscilloscope traces.
- Separate digital transition semantics from unmodeled physical timing parameters.
How It Works
The production D flip-flop has four inputs in this order: D, CLK, PRE, and CLR. With PRE = CLR = 0, a low-to-high transition on CLK stores the current D value in Q. Between rising edges, Q holds its previous state.
PRE and CLR are active-high asynchronous controls. CLR has highest priority and forces Q = 0. If CLR = 0 and PRE = 1, Q is forced to 1. Therefore PRE = CLR = 1 is not treated as an indeterminate state by this simulator; it deterministically clears Q because CLR is evaluated first.
Two output lights show Q and Q̅. The oscilloscope shows CLK and Q only. This is a digital behavioral model: it demonstrates state-transition priority but does not supply physical setup, hold, or propagation-delay measurements.
Truth Table
Representative state-transition cases for the production component. ↑CLK = 1 means that a rising edge occurs in the evaluated transition; Qₙ is the previously stored state.
| Inputs | Output | |||||
|---|---|---|---|---|---|---|
| CLR | PRE | ↑CLK | D | Q_n | Q_{n+1} | |
| 1 | 0 | 0 | 1 | 1 | 0 | CLR asynchronously clears Q. |
| 1 | 1 | 1 | 1 | 1 | 0 | CLR retains priority when PRE is also asserted. |
| 0 | 1 | 0 | 0 | 0 | 1 | With CLR low, PRE asynchronously sets Q. |
| 0 | 0 | 1 | 0 | 1 | 0 | A rising edge captures D = 0. |
| 0 | 0 | 1 | 1 | 0 | 1 | A rising edge captures D = 1. |
| 0 | 0 | 0 | 0 | 0 | 0 | Without a rising edge, a stored 0 is held. |
| 0 | 0 | 0 | 1 | 1 | 1 | Without a rising edge, a stored 1 is held. |
Boolean Expression
Active-high CLR has highest priority and asynchronously forces Q low.
With CLR low, active-high PRE asynchronously forces Q high.
When neither asynchronous control is asserted, a rising clock edge copies D into Q.
With both asynchronous controls low and no rising edge, the stored state is retained.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1CLK=single rising edgeCLR=0D=1PRE=0Expected:
Q = 1 and Q̅ = 0 after the rising edgeWhat you'll see:First set PRE and CLR low. Present D = 1 at a rising edge and compare the complementary output lights. - 2CLK=no new rising edgeCLR=0D=0PRE=0Expected:
Q remains 1 because no rising edge occursWhat you'll see:Change D to 0 without producing a new rising edge. Q remains at the value stored in step 1. - 3CLK=any levelCLR=0PRE=1Expected:
PRE forces Q = 1 without waiting for a clock edgeWhat you'll see:Assert PRE while CLR is low. Q goes high independently of the clock level. - 4CLK=any levelCLR=1PRE=1Expected:
CLR wins over PRE and forces Q = 0What you'll see:Keep PRE high and assert CLR. Q goes low, demonstrating the simulator's explicit clear-over-preset priority.
Components Used
Applications and Design Context
Register banks. Small or synthesized register banks may use parallel D flip-flops with clocked write-enable logic; larger register files can instead use dedicated memory structures.
Pipeline stages. A conventional five-stage pipeline commonly places four banks of state elements between adjacent stages. At a clock edge for which a bank's load or write enable is asserted, that bank transfers its input to its output; actual pipeline organizations vary.
Synchronous state machines. An FSM state register can use D flip-flops so that a clock edge replaces the current state with the next-state logic's result.
Interface registers. D flip-flops register signals that already satisfy the receiving clock domain's timing requirements. Asynchronous clock-domain crossings additionally require an appropriate synchronizer, handshake, or asynchronous FIFO.
FIFO storage. Small FIFOs may use flip-flop-based register rows, whereas larger implementations commonly use SRAM or FPGA block RAM plus pointer and control logic.
Frequently Asked Questions
Why is the D flip-flop edge-triggered instead of level-sensitive?
With PRE = CLR = 0, D is sampled only on a rising clock edge. Logic-level changes on D between rising edges do not update the stored Q state.
How do PRE and CLR behave in this component?
PRE and CLR are active-high asynchronous controls. PRE sets Q to 1; CLR resets Q to 0. They act without a clock edge, and CLR has priority if both are high.
Does this template model physical flip-flop timing?
No. It implements digital state transitions but does not characterize setup time, hold time, clock-to-Q delay, metastability, or analog waveforms.
Which outputs are visible?
One light is connected to Q and the other to Q̅. The oscilloscope receives CLK on channel 1 and Q on channel 2; Q̅ is not connected to the scope.
Does CLK = 1 continuously capture D?
The production component is explicitly rising-edge triggered. A steady high clock level is not a sequence of edges; after the transition to high has been processed, further D changes do not alter Q until a later low-to-high transition.