4-Bit Counter with Hexadecimal Display
A 4-bit enabled up-counter advances modulo 16, supports asynchronous clear, and drives one hexadecimal digit display. The two-channel scope observes clock and Q0; the circuit does not contain four output lights or a separate seven-segment display.
What You'll Learn
- Count upward modulo 16 under EN control.
- Use active-high asynchronous CLR to initialize the count.
- Interpret Q3..Q0 as a hexadecimal digit.
- Compare CLK and Q0 on the two oscilloscope channels.
- Identify the exact display components present in the production topology.
How It Works
The four-bit COUNTER receives CLK, active-high CLR, and active-high EN. Its reserved LD input is tied to logic 0. With CLR = 0 and EN = 1, each rising edge increments the count modulo 16. EN = 0 holds the stored value. CLR = 1 asynchronously forces the count to 0.
Q0..Q3 drive one DIGIT_DISPLAY, which represents the binary word as a hexadecimal digit from 0 through F. A separate two-channel oscilloscope receives CLK and Q0. During continuous enabled counting, Q0 toggles at every rising clock edge and completes one full cycle for every two clock periods, so its frequency is half the clock frequency.
The production topology contains neither four binary output lights nor a separate SEVEN_SEGMENT_DISPLAY component. All numeric presentation comes from the one digit-display primitive.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1CLR=1Expected:
The display becomes 0 immediatelyWhat you'll see:Assert CLR. The display changes to 0 without waiting for a clock edge. - 2CLR=0Clock=runningEN=1Expected:
The display advances 0, 1, …, F, then wraps to 0What you'll see:Release CLR and set EN = 1. Observe the hexadecimal sequence through F. Q0 toggles at each enabled rising edge and completes a full waveform period every two count increments. - 3CLR=0Clock=runningEN=0Expected:
The display and Q0 trace hold their current stateWhat you'll see:Set EN = 0. The display and Q0 hold even though CLK continues on channel 1. - 4CLR=0Clock=running at count 7EN=0Expected:
The display remains at 7 until EN is reassertedWhat you'll see:Pause at display value 7 with EN = 0. Additional clock edges leave the value at 7 until EN returns to 1.
Components Used
Applications and Design Context
Event-count demonstrations. A four-bit counter gives a compact 0–F view of incoming clock events.
Frequency division. During continuous enabled counting, Q0 toggles on every rising clock edge and has half the clock frequency; higher-order bits divide by successive powers of two.
Address sequencing. A modulo-16 counter can enumerate a small address space when an enabled sequential source is sufficient.
Digital instrumentation. A hexadecimal readout and waveform trace provide numeric and temporal views of the same state.
Frequently Asked Questions
Why can the display show A–F?
The DIGIT_DISPLAY interprets Q3..Q0 as one hexadecimal digit. Values 10 through 15 are therefore presented as A through F.
How does CLR operate?
CLR is active high and asynchronous. It forces the counter to 0 independently of CLK and EN.
How does EN operate?
EN is sampled for the rising-edge count operation. EN = 1 increments; EN = 0 holds. The clock can continue toggling while the count is paused.
Does this circuit contain binary lights or a separate seven-segment display?
No separate seven-segment display or output-light components are present. One DIGIT_DISPLAY receives all four bits directly.
Which signals are on the oscilloscope?
The two-channel scope receives CLK and Q0. Q1, Q2, and Q3 are visible through the hexadecimal display only.