4-Bit Counter with Display Circuit Simulator

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Enable JavaScript to load the live circuit. The truth table below describes the circuit's behaviour.

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What You'll Learn

Combine a counter with a display decoder to show counts visually.
Recognize the counter-display pattern as combining sequential and combinational logic.
See decimal/hex digit conversion from binary.
Apply this architecture to clocks, score displays, and lab counters.
Cascade multiple counter+display units for multi-digit numeric output.

How It Works

A 4-bit counter with display combines a synchronous 4-bit counter with a 7-segment-style digit display, showing the count as a decimal value (or hex digit, since 4 bits = 0–F).

The display decoder converts the 4-bit binary count into a 7-segment pattern: which segments light up to form each digit shape. For values 0–9 it shows the decimal digit; for 10–15 it typically shows hex letters A, B, C, D, E, F.

This is the classic counter+display demonstration used in introductory digital labs. It's also the same architecture used in real digital clocks (multiple counters cascaded with displays), event counters, and stopwatches.

The display behaviour is combinational — it depends only on the current counter value. The counter itself is sequential — it depends on history (clock edges). Together they form the basic building block of any digital instrument with a numeric readout.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

Clock = running slowly

Expected: Display cycles through 0..F

What you'll see: Watch the display increment on each clock edge: 0, 1, 2, ..., 9, A, B, C, D, E, F, then wrap back to 0.
2

Clock = stopped at 7

Expected: Display shows 7

What you'll see: Stop the clock — the display freezes at the current count value. Counter is sequential; display is combinational.
3

Clock = fast

Expected: Display cycles too fast to read

What you'll see: At high clock rates the digits blur — real human-readable counters use slow clocks (Hz range) or are sampled into a refresh buffer.
4

Reset = 1

Expected: Display jumps to 0

What you'll see: Asserting reset clears the counter. Display immediately reflects the new 0 value.

Components Used

Real-World Applications

Lab event counters. Bench instruments displaying pulse counts use exactly this architecture — counter + display.

Digital clocks. Each digit (hours, minutes, seconds) is its own counter with its own display, cascaded with carry-out triggering the next-larger digit.

Score displays in arcade games. Each digit is a counter+display; scoring increments the counter; the display refreshes each clock cycle.

Timing instrumentation. Frequency counters, period meters, and stopwatches all use cascaded counters with multi-digit displays.

Hexadecimal viewers. Memory dump displays (like in early debuggers) used 7-segment hex displays to show byte values — 4-bit counter values become hex digits A-F.

Frequently Asked Questions

Why does the display show A-F for values 10-15?

4 bits can encode 16 values (0–15). The first 10 are written 0–9; the next 6 are conventionally A–F in hexadecimal. 7-segment decoders can be designed for either decimal-only (showing blank or error for 10+) or hex (showing A–F).

Could I make this count in BCD instead of binary?

Yes — a BCD counter resets to 0 after reaching 9 instead of going to A. This requires extra logic detecting count = 1010 and asynchronously resetting. BCD counters are common in clock and meter applications.

How would I display two-digit numbers (00–99)?

Cascade two BCD counters with displays. The ones digit counts 0–9; on its rollover from 9 to 0, it generates a carry that increments the tens digit. Each digit has its own display.

What's the role of the 7-segment decoder?

It maps each 4-bit input value to a 7-bit pattern indicating which segments to light. Encoded as a fixed truth table or in lookup-table form. Most digital simulators include it as a primitive, hiding the decode logic.

Is the display update synchronous with the clock?

The counter updates on the clock edge; the decoder is combinational and updates immediately when the counter changes (with small propagation delay). So the display effectively updates one gate-delay after each clock edge.