8-Bit SIPO Shift Register Circuit Simulator

Fig. 1 — 8-Bit SIPO Shift Register INTERACTIVE

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What You'll Learn

Use an 8-bit SIPO register to assemble a byte from a serial bit stream.
Recognize the 8-clock latency for full byte reception.
Connect SIPO registers to SPI, I²C, and other serial protocols.
Identify 74xx164/595 ICs as commercial 8-bit SIPO implementations.
Apply SIPO for GPIO expansion and ADC serial output decoding.

How It Works

An 8-bit SIPO (Serial-In Parallel-Out) shift register is the standard byte-receiving primitive for serial buses. Eight D flip-flops chained: serial data in on one wire, parallel output on 8 wires. After 8 clock cycles, one byte has been fully shifted in and is available simultaneously on Q7..Q0.

The canonical example: an SPI receiver. Each clock edge, the master sends one bit on MOSI; the slave's SIPO register captures it. After 8 clocks, the slave's parallel output holds the received byte, ready for the rest of the slave's logic to use.

The 74xx164 and 74xx595 are classic TTL/CMOS chips that implement exactly this — 8-bit SIPO with optional output latches. They're widely used to expand microcontroller GPIO via 3-wire interfaces.

Key timing: serial input must be stable around each clock edge. The byte is fully assembled and stable on the parallel outputs immediately after the 8th clock edge — usable from cycle 8 onward without waiting.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

Serial = 00000000 Clock = 8 edges

Expected: Q = 00000000

What you'll see: All-zero stream — register fills with zeros. Parallel output = 0.
2

Serial = 10101010 Clock = 8 edges

Expected: Q = 10101010

What you'll see: Alternating pattern — after 8 clocks the register holds the full alternating byte. Each bit's position depends on shift direction (MSB-first or LSB-first).
3

Serial = 11111111 Clock = 8 edges

Expected: Q = 11111111

What you'll see: All-ones stream — after 8 clocks register is full of 1s. Parallel output = 0xFF.
4

Serial = 01000001 Clock = 8 edges

Expected: Q = 01000001 (= 65 = 'A' in ASCII)

What you'll see: Specific pattern — after 8 clocks the byte 0x41 is on the parallel output. This is how a UART would receive the letter 'A'.

Components Used

Shift Register (8-bit)

Real-World Applications

SPI/I²C byte reception. Each transaction shifts 8 bits in serially; the SIPO register reassembles them as a byte for the receive FIFO.

74xx595 LED driver. A microcontroller controls many LEDs through a 3-wire SPI link to a 595; the 595's SIPO output drives the LEDs in parallel.

ADC serial output decoding. Many ADCs serialize their conversion result; the host shifts the bits into a SIPO and reads the parallel value.

RFID and 1-Wire protocol decoders. Bit-banged serial protocols use SIPO registers to assemble multi-bit fields from the bit stream.

Test scan-out paths. DFT scan chains end at SIPO registers that capture multi-bit signature values for analysis.

Frequently Asked Questions

MSB-first or LSB-first shifting?

Either is possible — the register's wiring determines which. SPI is typically MSB-first; UART is LSB-first. The shift register itself is symmetric; the choice is a configuration decision.

When can I read the parallel output?

Any time, but the value is meaningful only after enough clocks have shifted in valid data. For an 8-bit byte, that's after 8 clock edges. Reading mid-shift gives a mix of old and new bits.

How do I know when the byte is complete?

Count the clocks. Most systems use a separate counter to assert a 'byte ready' strobe after 8 clock cycles. Alternatively, a chip-select line frames the byte transmission, and the receiver knows the byte is complete when chip-select releases.

What's the parallel-load capability?

Pure SIPO doesn't have parallel load. Universal shift registers do — they can switch between shift and parallel-load modes via a control signal. Useful when you want to seed the register with a known value before shifting.

How fast can SIPO registers run?

Limited by the slowest flip-flop's clock-to-Q + setup. Modern CMOS SIPOs run at multi-GHz; specialty SerDes circuits push beyond using internal clock recovery and parallel processing.