8-Bit SIPO Shift Register
An 8-bit register shifts SI toward Q0 on each rising clock edge with direction and mode fixed LOW. One scope shows SI and clock, while an 8-channel scope shows Q0..Q7; SO is not connected.
What You'll Learn
- Use an 8-bit SIPO register to assemble a byte from a serial bit stream.
- Trace the exact DIR = 0 transition from Q7 toward Q0.
- Convert between chronological SI order and Q7..Q0 word order.
- Use separate scopes for SI/CLK and the eight parallel outputs.
- Distinguish connected Q outputs from the unconnected SO pin.
How It Works
The SHIFT_REGISTER_8BIT receives SI and CLK from an input switch and clock generator. A logic-0 constant drives both DIR and S/L. According to the production evaluator, DIR = 0 shifts toward Q0: on each rising edge, Q0 ← Q1, Q1 ← Q2, …, Q6 ← Q7, and Q7 ← SI. S/L = 0 selects that serial-shift operation instead of parallel load.
After eight rising edges, the register contains the eight SI values, with the earliest value at Q0 and the latest at Q7. Therefore, to form the displayed word Q7..Q0 = 10101010, the chronological SI sequence is 0, 1, 0, 1, 0, 1, 0, 1.
A two-channel scope shows SI then CLK. A separate 8-channel scope shows Q0..Q7. The serial SO pin is not connected. This circuit presents ideal digital state evolution rather than analog timing performance.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1Clock=8 rising edgesSI=0, 0, 0, 0, 0, 0, 0, 0Expected:
Q7..Q0 = 00000000What you'll see:Shift eight zeros to establish a known state independently of the saved register contents. - 2Clock=8 rising edgesSI=0, 1, 0, 1, 0, 1, 0, 1Expected:
Q7..Q0 = 10101010What you'll see:Present 0,1,0,1,0,1,0,1 in chronological order. The final Q7..Q0 trace values form 10101010. - 3Clock=8 rising edgesSI=1, 1, 1, 1, 1, 1, 1, 1Expected:
Q7..Q0 = 11111111What you'll see:Eight ones replace every prior bit, producing Q7..Q0 = 11111111. - 4Clock=8 rising edgesSI=1, 0, 0, 0, 0, 0, 1, 0Expected:
Q7..Q0 = 01000001 (0x41)What you'll see:Present 1,0,0,0,0,0,1,0 chronologically. Reversing that arrival order across Q7..Q0 yields 01000001.
Components Used
Applications and Design Context
Serial receivers. A SIPO stage reconstructs a parallel word when an external protocol supplies suitable clocking and framing.
GPIO expansion. Serially delivered control bits are available in parallel after the complete word has arrived. Because this primitive has no separate output latch, its Q outputs change during shifting; applications that require a simultaneous visible update need an additional latch or equivalent output-enable strategy.
Converter interfaces. Serial ADC or sensor bits may be assembled for parallel processing.
Test and scan paths. Exposing every stored bit helps inspect a shifted test sequence.
Frequently Asked Questions
What bit order does this saved circuit use?
DIR is tied to 0. In the production evaluator, that means SI enters Q7, while existing bits move Q7 → Q6 → … → Q0. To obtain a stated Q7..Q0 word after eight edges, present its bits chronologically from Q0 toward Q7.
Which operating mode is selected?
S/L is tied to 0, selecting serial-shift mode. The D0..D7 parallel inputs are disconnected and ignored in this configuration.
How are the scope channels assigned?
The 2-channel scope receives SI on channel 1 and CLK on channel 2. The 8-channel scope receives Q0 through Q7 in that order.
Is the serial output observed?
No. The SHIFT_REGISTER_8BIT has an SO pin, but that pin has no connection in this production circuit. All eight parallel Q outputs are connected.
Can this template establish a maximum shift frequency?
No. The scopes display the simulator's resolved digital states. They do not characterize setup, hold, clock-to-Q delay, or analog signal integrity.