4-Bit Combination Lock (1011)
Four XNOR comparisons and a two-level AND tree assert the output only when the switch word equals the stored reference 1011. One disconnected HIGH constant is present but cannot affect the result.
What You'll Learn
- Explain why XNOR implements 1-bit equality comparison.
- Derive the 4-bit equality expression from the comparator outputs.
- Trace the two-level AND tree from individual matches to UNLOCK.
- Verify from the complete truth table that only 1011 is accepted.
- Determine the worst-case gate depth from an input switch to the output lamp.
- Distinguish an instructional fixed-word detector from a secure access-control system.
How It Works
This circuit is a 4-bit equality detector presented as a combination lock. For analysis, label the four input switches from top to bottom A, B, C, and D. Four constants store the reference word 1011. Each XNOR gate compares one switch with one stored bit and produces a HIGH match signal only when the two values are equal.
The four match signals feed a balanced, two-level AND tree. The first two AND gates test the upper and lower bit pairs; the final AND gate combines those pair results. Consequently, the UNLOCK lamp is HIGH if and only if all four comparisons succeed. The implemented function reduces to A · B̅ · C · D, so exactly one of the 16 possible input vectors is accepted.
From any switch to the lamp, the longest path contains one XNOR stage followed by two AND stages. The corresponding worst-case propagation depth is therefore three gate delays, excluding interconnect delay. The saved schematic also contains one disconnected logic-HIGH constant; it is counted in the component metadata but cannot affect the output.
Truth Table
The reference word is 1011. UNLOCK is HIGH only when A=1, B=0, C=1, and D=1; every other input vector contains at least one mismatch.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| A | B | C | D | UNLOCK | |
| 0 | 0 | 0 | 0 | 0 | A, C, and D differ from the stored word. |
| 0 | 0 | 0 | 1 | 0 | A and C differ from the stored word. |
| 0 | 0 | 1 | 0 | 0 | A and D differ from the stored word. |
| 0 | 0 | 1 | 1 | 0 | Only A differs from the stored word. |
| 0 | 1 | 0 | 0 | 0 | All four bits differ from the stored word. |
| 0 | 1 | 0 | 1 | 0 | A, B, and C differ from the stored word. |
| 0 | 1 | 1 | 0 | 0 | A, B, and D differ from the stored word. |
| 0 | 1 | 1 | 1 | 0 | A and B differ from the stored word. |
| 1 | 0 | 0 | 0 | 0 | C and D differ from the stored word. |
| 1 | 0 | 0 | 1 | 0 | Only C differs from the stored word. |
| 1 | 0 | 1 | 0 | 0 | Only D differs from the stored word. |
| 1 | 0 | 1 | 1 | 1 | All four bits match 1011; UNLOCK is HIGH. |
| 1 | 1 | 0 | 0 | 0 | B, C, and D differ from the stored word. |
| 1 | 1 | 0 | 1 | 0 | B and C differ from the stored word. |
| 1 | 1 | 1 | 0 | 0 | B and D differ from the stored word. |
| 1 | 1 | 1 | 1 | 0 | Only B differs from the stored word. |
Boolean Expression
Each XNOR output is HIGH precisely when its input bit equals the corresponding stored bit.
The two-level AND tree asserts UNLOCK only when all four comparison results are HIGH. Substituting the stored word 1011 gives the equivalent minterm.
Try It Step-by-Step
Set the listed controls in the embedded circuit, then compare the observed modeled state with the expected result.
- 1A=0B=0C=0D=0Expected:
UNLOCK = 0What you'll see:With 0000 applied, only the second-bit comparison matches. The AND tree therefore keeps UNLOCK LOW. - 2A=1B=0C=1D=1Expected:
UNLOCK = 1What you'll see:All four XNOR outputs are HIGH for 1011, so both pair results and the final UNLOCK output become HIGH. - 3A=1B=0C=1D=0Expected:
UNLOCK = 0What you'll see:Changing only D to 0 drives the fourth XNOR output LOW and immediately blocks the lower pair. - 4A=1B=1C=1D=1Expected:
UNLOCK = 0What you'll see:Changing only B to 1 creates a mismatch against the stored 0, which keeps UNLOCK LOW. - 5A=0B=0C=1D=1Expected:
UNLOCK = 0What you'll see:Although the final three bits match, A=0 fails the first comparison, so the candidate word is rejected.
Components Used
Applications and Design Context
Digital comparators. Equality outputs in processors, bus interfaces, and verification logic use the same bitwise-XNOR followed by reduction-AND structure.
Address and identifier recognition. Hardware can detect one configured address, device ID, instruction field, or protocol symbol by comparing every bit in parallel.
Interlocks and configuration checks. A controller may enable an operation only when several binary configuration inputs exactly match an authorized operating mode.
Pattern detectors. Parallel equality networks recognize fixed words in communication and test equipment; sequential detectors extend the idea to patterns arriving over time.
Educational lock models. A fixed combination makes equality logic easy to observe, while also demonstrating why visible combinational logic alone is not secure authentication.
Frequently Asked Questions
Why does the circuit use XNOR gates?
XNOR is an equality function: its output is HIGH when both inputs have the same logic value. That makes one XNOR gate a direct 1-bit comparator.
Why is 1011 the only word that unlocks the circuit?
The four constants store 1, 0, 1, and 1. Every XNOR output must be HIGH before the final AND gate can assert UNLOCK, so 1011 is the only accepted input vector.
What is the purpose of the AND tree?
A balanced tree combines four match signals with 2-input gates: two AND gates evaluate the pairs, and a third combines those results. This structure implements a 4-input conjunction without requiring a 4-input gate.
What is the circuit's propagation depth?
A change at any switch passes through one XNOR gate and two AND-gate levels before it reaches UNLOCK. Ignoring wire delay, the worst-case path is therefore three gate delays.
How can this equality detector be extended to more bits?
Use one XNOR comparator per bit and combine every match result with an AND tree. A balanced tree keeps the number of AND-gate levels logarithmic in the word width.
Is this circuit suitable as a real security lock?
No. The fixed word and gate connections are visible, so this circuit is an instructional equality detector, not a secure authentication mechanism. Practical access control requires protected credentials and sequential control logic.