CPU Flags Register Circuit Simulator

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Lo que aprenderás

Identify the four most-common CPU flags: Z, N, C, V.
Understand how each flag is computed from ALU output bits.
Connect flag values to conditional branch instructions.
Recognize that the flags register is a small parallel D-flip-flop bank.
Apply flags for multi-precision arithmetic and conditional execution.

Cómo funciona

A CPU flags register (or status register, condition code register) stores Boolean status bits updated by the ALU after each operation. The most common flags: - Z (Zero): Set when the ALU result is zero. - N (Negative / Sign): Set when the result's high bit is 1 (negative in two's complement). - C (Carry): Set when an unsigned operation produces a carry-out. - V (Overflow): Set when a signed operation overflows the representable range.

Each flag is a single D flip-flop, clocked synchronously with the ALU result. The next-state logic is derived from the ALU output: - Z_next = NOR-reduce of all result bits. - N_next = result high bit. - C_next = ALU carry-out. - V_next = computed from sign-bit logic.

Conditional branch instructions read these flags to decide whether to jump: - BEQ (branch-if-equal): tests Z = 1 (subtract gave zero, so operands were equal). - BNE: tests Z = 0. - BMI (branch-if-minus): tests N = 1. - BCS, BCC: test C. - BVS, BVC: test V.

On x86, the flags register is called EFLAGS / RFLAGS and includes ~12 flags. On ARM, it's CPSR. RISC-V minimizes flags by using compare-and-branch instructions that test conditions directly. Different architectures, same flags concept.

Pruébalo paso a paso

Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.

1

Result = 00000000 Carry = 0

Esperado: Z=1, N=0, C=0, V=0

Lo que verás: Result is zero — Z flag fires. All other flags clear. This pattern appears after operations that cancel out (e.g., A − A = 0).
2

Result = 10000000 Carry = 0

Esperado: Z=0, N=1, C=0, V=0

Lo que verás: High bit set — N flag fires (negative in two's complement). Decimal value -128. Branch-if-minus would jump.
3

Result = 11111111 Carry = 1

Esperado: Z=0, N=1, C=1

Lo que verás: Result is -1 (or 255 unsigned) and operation produced a carry-out. C flag fires for multi-precision continuation.
4

Result = 01111111 + 1 = 10000000 Op = ADD

Esperado: Z=0, N=1, V=1

Lo que verás: Adding 1 to 127 (max positive in signed 8-bit) gives -128 — signed overflow. V flag fires; the result is wrong if interpreted as signed.

Componentes utilizados

Aplicaciones en el mundo real

Conditional branches. Every "if" statement in compiled code becomes a comparison + flag update + conditional branch. The flags register is the bridge between ALU and branch logic.

Multi-precision arithmetic. Adding 256-bit numbers on a 64-bit CPU uses ADC (add-with-carry) — each chunk's carry-out feeds the next chunk's carry-in via the C flag.

Polling vs. flag-based state machines. Some peripherals expose status as flag-like bits in registers; firmware polls these flags to determine when to act.

Saturating arithmetic in DSP. A DSP using the V flag can clamp results to max/min instead of wrapping — essential for audio processing where wraparound creates harsh distortion.

Compiler optimization. Optimizing compilers carefully manage flag dependencies — reordering instructions across flag-clobbering operations breaks branch correctness. ABI specs document which instructions clobber which flags.

Preguntas frecuentes

Why have separate carry and overflow flags?

Carry tracks unsigned arithmetic (did we exceed 2^N − 1?); Overflow tracks signed arithmetic (did we exceed 2^(N-1) − 1 or go below -2^(N-1)?). Both are sometimes set, sometimes only one — they're independent because unsigned and signed interpretations differ.

How is the zero flag computed?

NOR-reduce all result bits — high only when every bit is 0. Equivalent to NOT(OR-reduce). Modern CPUs compute Z in parallel with the ALU result so it's available for branch testing in the same cycle.

What's the propagation delay from ALU to flag register?

The flag-compute logic adds 1–2 gate delays after the ALU output. With careful design, the flags are stable in time for the next clock edge to capture them. Pipelined CPUs may hold flags for multiple cycles to handle dependent branches.

What's an 'unaffected' flag?

Some instructions update only some flags. For example, ADD updates Z, N, C, V; XOR updates Z, N but not C or V. The unaffected flags retain their old values. Compilers know which instructions clobber which flags and schedule accordingly.

How does ADC (add-with-carry) use the C flag?

ADC computes A + B + C, where C is the previous operation's carry-out. By chaining ADD-then-ADC, you can add multi-precision integers: each chunk uses ADD or ADC to incorporate the carry from the chunk below.