Flags Register
Use DigiSim's Flags Register to capture Z, C, N, and V inputs on a rising CLK edge when LD=1. Active-HIGH CLR clears all four stored outputs asynchronously.
Overview
The Flags Register stores four CPU condition bits: zero, carry/borrow, negative, and overflow.
Exact DigiSim.io Implementation
| Pin | Role |
|---|---|
| Z_in, C_in, N_in, V_in | Flag data inputs. |
| LD | Active-HIGH synchronous load enable. |
| CLK | Rising-edge clock. |
| CLR | Active-HIGH asynchronous clear. |
| Z_out, C_out, N_out, V_out | Stored flags; always driven. |
Usage Notes
- CLR has priority and acts without a clock edge.
- The pin order is exactly the order shown above; there is no generic “Flag In” pin.
- Outputs do not have an OE control and never intentionally enter high-impedance.
Learning Path
Prerequisites
Next Steps
Frequently Asked Questions
What is a flags register?
The component stores four independent input bits: Zero, Carry/borrow, Negative, and Overflow. Its outputs are always driven; it does not calculate flags or provide output enable.
How are flags used in branching?
DigiSim's built-in Control Unit implements JZ when the Zero flag is 1 and JNZ when it is 0. Carry, Negative, and Overflow remain available as stored outputs for external logic, but the built-in conditional branches do not consume them.