Shift Register (8-bit)
Use DigiSim's 8-bit Shift Register for rising-edge parallel load or bidirectional serial shift. S/L=1 loads D0–D7; S/L=0 shifts according to DIR.
Overview
The 8-bit Shift Register supports rising-edge parallel load or bidirectional serial shift with parallel and serial outputs.
Exact DigiSim.io Implementation
| Pin | Role |
|---|---|
| SI | Serial input. |
| CLK | Rising-edge clock. |
| DIR | 1 = left; 0 = right. |
| S/L | 1 = parallel load; 0 = serial shift. |
| D0–D7 | Parallel data inputs. |
| Q0–Q7, SO | Parallel outputs and serial output. |
Usage Notes
- The register changes only on a rising CLK edge.
- There is no CLR, OE, or separate hold pin. With S/L = 0, every rising edge shifts; with S/L = 1, every rising edge loads.
- Q0–Q7 and SO are always driven.
Learning Path
Prerequisites
Next Steps
Frequently Asked Questions
Where are 8-bit shift registers used?
Use it to inspect serial-to-parallel and parallel-to-serial data movement. It is a generic register model, not a complete SPI or UART interface and not an LFSR unless external feedback logic is added.
How do DIR, SI, and SO behave?
With S/L=0, DIR=1 shifts left so SI enters Q0 and SO reflects Q7; DIR=0 shifts right so SI enters Q7 and SO reflects Q0. A shift occurs on every rising CLK edge in this mode, and the component has no CLR, OE, or separate hold input.