T Flip-Flop Frequency Divider Circuit Simulator

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JavaScript を有効にするとライブ回路が読み込まれます。下の真理値表で動作を確認できます。

学べること

Use a T flip-flop in toggle mode to divide a clock by 2.
Recognize that output frequency = clock frequency / 2 in toggle mode.
Cascade T flip-flops for division by higher powers of 2.
Connect this to crystal-based watch and clock circuits.
Distinguish T from JK and D flip-flops by use case.

仕組み

A T flip-flop ('toggle flip-flop') has a single input T and a clock. When T = 1 and a clock edge arrives, Q flips to its complement. When T = 0, Q holds. With T tied permanently to 1, the flip-flop toggles on every active clock edge — producing an output square wave at exactly half the clock frequency.

This divide-by-2 behaviour is the heart of every binary counter. Cascading N T flip-flops (each clocked by the previous Q) divides the input frequency by 2ⁿ — the cascading ripple counter pattern.

T flip-flops can be built from JK (J=K=T) or D flip-flops (D = T XOR Q). Most cell libraries provide all three primitives; synthesis tools pick whichever maps best to the available cells.

A single T flip-flop's role as a divide-by-2 stage is the simplest possible frequency synthesis primitive. Used in clock generators, watch ICs, audio sample-rate dividers, and any context where you need a slower clock derived from a faster master oscillator.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

T = 1 Clock = running at 1 Hz

期待値: Q toggles at 0.5 Hz

観察ポイント: Watch the output light blink at half the clock rate. Each clock edge flips Q.
2

T = 1 Clock = running at 100 Hz

期待値: Q toggles at 50 Hz

観察ポイント: Faster clock → faster output, but always half. The divide ratio is fixed at 2.
3

T = 0 Clock = running

期待値: Q frozen

観察ポイント: T = 0 means hold mode. Clock edges arrive but Q doesn't change. The flip-flop ignores the clock when T is low.
4

T = varying Clock = running

期待値: Q toggles only when T was 1 at the edge

観察ポイント: Edge-triggered behaviour: T's value matters at the clock edge, not in between. Toggle T while clock is high — no immediate effect; wait for the next edge.

使用コンポーネント

実世界での応用

Watch crystal dividers. A 32.768 kHz watch crystal feeds a 15-stage T flip-flop chain (divide by 2¹⁵ = 32768) to produce a 1 Hz second tick.

Clock domain step-down. A 1 GHz CPU clock can be divided to 500 MHz, 250 MHz, etc. for slower peripheral domains using T flip-flops.

Ripple binary counters. Each bit of a binary counter is a T flip-flop in toggle mode, with the previous bit's Q acting as its clock. Bit 0 toggles every input edge; bit 1 every other; etc.

PWM frequency generation. Audio and motor PWM generators divide the system clock to a target PWM frequency using a T-divider chain.

Test signal generation. Bench signal generators use programmable T-divider chains to produce a wide range of clock frequencies from a single master oscillator.

よくある質問

Why is divide-by-2 so common?

Because it's the simplest stable division you can do with a single flip-flop. Other ratios (divide by 3, 5, etc.) require more complex feedback. Binary counters naturally produce powers-of-2 division by chaining toggle stages.

How do I divide by 4? By 8?

Cascade T flip-flops: 2 stages → divide by 4; 3 stages → divide by 8. Each new stage is clocked by the previous stage's Q output, so each adds another factor of 2.

What's the difference between divide-by-2 and divide-by-2 with 50% duty cycle?

T flip-flop toggle naturally produces 50% duty cycle (Q is high for one full clock cycle, low for the next). Other dividers (e.g., divide-by-3) often produce non-50% outputs unless extra logic balances the duty cycle.

Is the divided clock perfectly aligned with the input clock?

No — it's offset by the flip-flop's clock-to-Q propagation delay (typically 50–500 ps in CMOS). For most applications this is negligible; for tight timing you can use registered output buffers to align edges to the next clock.

How is this different from a phase-locked loop (PLL)?

A T-divider creates exact integer divisions of the input. A PLL can multiply or divide by fractional ratios using a feedback loop. PLLs are more complex but allow non-integer divides; T-dividers are simpler but limited to powers of 2 (or integer divides with extra decode logic).