Register Data Transfer System Circuit Simulator

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学べること

Move data between registers using a shared bus.
Use tri-state buffers to arbitrate which register drives the bus.
Apply LOAD signals to capture bus data into destination registers.
Recognize this as the foundational architecture of CPU register files.
Trace a single-cycle register-to-register transfer step by step.

仕組み

A register data transfer system demonstrates how multiple registers share a common bus for moving data. This is the core architecture inside every CPU's register file: many registers, one (or a few) bus(es), with arbitration logic to ensure exactly one register drives the bus at any moment.

Key components: - Source register read: Each register has a tri-state output buffer (or MUX channel) gated by a read-enable. Asserting READ on register A drives A's contents onto the bus. - Destination register write: Each register has a load-enable input. Asserting LOAD on register B captures the bus value into B on the next clock edge. - Tri-state arbitration: Only one register's READ should be active at a time, otherwise multiple drivers conflict on the bus.

A single-cycle transfer: 1. Cycle starts; bus is at high-Z. 2. Source register's READ asserts → its data drives the bus. 3. Destination register's LOAD asserts → on the rising clock edge, dst captures the bus. 4. READ and LOAD release; bus returns to high-Z.

This is the micro-architectural foundation of CPU register files: every move instruction (MOV, LD, ST, etc.) ultimately decomposes into reads of source registers, computation, and writes to destination registers — all over shared internal buses.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

Reg A = 1010 READ_A = 1 LOAD_B = 1 Clock = rising

期待値: Reg B = 1010

観察ポイント: Step 1: READ_A asserts → A's contents drive the bus. Step 2: LOAD_B asserts → on clock edge, B captures the bus. After: B = 1010.
2

READ_A = 0 READ_B = 0

期待値: Bus = high-Z

観察ポイント: No reads active — bus floats. Real systems have weak pull-ups or pull-downs to default it to a known value.
3

READ_A = 1 READ_B = 1

期待値: Bus contention!

観察ポイント: Both registers driving simultaneously → contention. In real silicon this stresses the transistors and produces undefined behaviour. Always ensure exactly one driver is active.
4

Reg B = 0101 READ_B = 1 LOAD_A = 1 Clock = rising

期待値: Reg A = 0101

観察ポイント: Reverse direction — read B onto bus, load into A. Same architecture handles transfers in either direction.

使用コンポーネント

実世界での応用

CPU register-file design. Modern CPUs have register files supporting 2–4 reads and 1–2 writes per cycle. Same shared-bus pattern, just wider and faster.

DMA controllers. A DMA engine moves data between memory regions; conceptually it uses register-transfer logic with addresses and counters playing the role of source/dest registers.

Pipeline forwarding paths. When stage N+1 needs data from stage N's output before it's written back, forwarding multiplexers route the value across pipeline stages — a small register-transfer subsystem.

Microcontroller peripheral DMA. Peripherals' control registers move data from receive FIFOs to system RAM via internal buses with this pattern.

Educational simulators (e.g., MIPS). Teaching CPU architecture often starts with a register-transfer demonstration so students see how individual data movements compose into full instruction execution.

よくある質問

Why use a shared bus instead of point-to-point wires?

Wiring efficiency. With N registers, point-to-point would need N×(N-1) wires to allow any-to-any transfer. A shared bus needs just N wires (the bus itself) plus per-register tri-state controls. Big savings for large register files.

What's the role of the tri-state buffers?

Arbitration. Multiple registers connect to the bus, but only one drives at a time. Tri-state outputs let the active register push its data while others float to high-Z, avoiding contention. Without tri-state, this architecture wouldn't work — every register would always drive, conflicting.

Could I use a multiplexer instead of tri-state?

Yes — a multi-input MUX with read-enable as select can replace the tri-state arrangement. CPUs often use this for internal register reads because MUXes are easier to verify than tri-state contention. The trade-off is that the MUX scales as O(N×width); tri-state buffers are smaller but riskier.

How does a CPU instruction decode into register transfers?

An instruction like ADD R1, R2, R3 (R1 = R2 + R3) decomposes into: read R2 to bus A, read R3 to bus B, compute on the ALU, write the result to R1's bus. Modern CPUs have multiple buses to support multiple reads + writes per cycle.

What about pipeline hazards?

When a later instruction reads a register that an earlier instruction is still writing, the pipeline forwards the not-yet-written value via dedicated bypass buses to avoid stalling. Forwarding logic is essentially additional register-transfer paths added to the basic architecture.